component
PJ9350L28DE
Public Made by Adomby adom
PJSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-4L(1x1). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPJ9350L28DE
PJSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4L(1x1)
PJ9350L28DE from PJSEMI, in a DFN-4L(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output of the fixed 2.8 V variant (PJ9350L28DE); a minimum 1uF output capacitor is required for stability and the maximum output current is 300mA. |
| 2 | GND | power_in | Ground reference pin; input and output capacitors must return to a clean analog ground. |
| 3 | EN | input | Active-high chip enable with VENH minimum 1.2V, VENL maximum 0.4V, input current maximum 1.0uA, and the datasheet notes this pin is high impedance. |
| 4 | VIN | power_in | Power input with a supply range of 2.5V to 6.5V (absolute maximum -0.3V to 8V), which must stay above VOUT for the device to regulate. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | DFN-4L(1x1) |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.5 | 6.5 | V | 8 | ||
| Output Voltage Accuracy | ΔVOUT | -2 | 2 | % | VOUT ≥1.8V, IOUT=1mA | 8 | |
| Dropout Voltage | VDROP | 220 | 250 | mV | VOUT≥2.5V, IOUT=200mA | 8 | |
| Dropout Voltage | VDROP | 320 | 350 | mV | VOUT≥2.5V, IOUT=300mA | 8 | |
| Line Regulation | ΔVLINE | 0.01 | 0.15 | %/V | VIN=2.7~5.5V, IOUT=1mA | 8 | |
| Load Regulation | ΔVLOAD | 40 | 70 | mV | VOUT>1.8V, IOUT=1~300mA | 8 | |
| Standby Current | IStandby | 1 | μA | VEN=0 | 8 | ||
| EN Logic High Voltage | VENH | 1.2 | V | VIN=5.5V, IOUT=1mA | 8 | ||
| EN Logic Low Voltage | VENlL | 0.4 | V | VIN=5.5V, VOUT=0V | 8 | ||
| EN Input Current | IEN | 1 | μA | VEN= 0~5.5V | 8 | ||
| Maximum Input Voltage | -0.3 | 8 | V | 7 | |||
| Output Current | 400 | mA | 7 | ||||
| Power Dissipation | 550 | mW | DFN1x1-4L | 7 | |||
| Junction Temperature | -40 | 125 | °C | 7 | |||
| Storage Temperature Range | -55 | 150 | °C | 7 | |||
| Lead Temperature | 260 | °C | 10S | 7 | |||
| ESD Voltage HBM | 2 | kV | HBM | 7 | |||
| Supply Voltage | 2.5 | 6.5 | V | 7 | |||
| Maximum Output Current | 300 | mA | 7 | ||||
| Operating Ambient Temperature | -40 | 85 | °C | 7 | |||
| Thermal Resistance, Junction-to-Ambient | 180 | °C/W | DFN1x1-4L | 7 |
CAD (KiCad official)
- Symbol:
PJ9350L28DE - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN-4L(1x1) (KiCad packages3D, STEP)
- 3D model files:
pj9350l28de-etched.step/pj9350l28de-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pj9350l28de.step/pj9350l28de.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PJSEMI datasheet (18 pp, sha256
07d6b42aa3d8f2df, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).