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LT3800EFE#PBF
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Analog Devices DC-DC Controllers, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLT3800EFE#PBF
Analog Devices · DC-DC Controllers · TSSOP-16-EP
LT3800EFE#PBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Converter input supply; the IC operates from 4V to 60V input with UVLO start-up threshold of 7.5V. |
| 2 | NC | unconnected | No connection. |
| 3 | SHDN | input | Precision shutdown pin with 1.35V rising enable threshold and 120mV hysteresis; pulling it below 0.7V puts the IC in low-current shutdown with IVIN below 10μA. |
| 4 | CSS | input | Soft-start AC coupling capacitor input, connected in series with a 200k resistor to VOUT, with 2μA average current setting the output startup slew rate; shorting it to SGND disables soft-start. |
| 5 | BURST_EN | input | Burst Mode and reverse-current inhibit enable: below 0.5V both functions are enabled, and reverse-current inhibit is disabled above 2.5V. |
| 6 | VFB | input | Error amplifier inverting input connected to the internal 1.231V reference through a resistive divider from VOUT, with 25nA typical input bias current. |
| 7 | VC | passive | Error amplifier output corresponding to peak switch current per cycle, which must not be pulled low with a low-impedance source and should be bypassed by at least 100pF; external manipulation requires a 1kΩ series resistance. |
| 8 | SENSE- | input | Negative input of the current sense amplifier, with inductor current limit set at ±150mV across the SENSE inputs. |
| 9 | SENSE+ | input | Positive input of the current sense amplifier, with inductor current limit set at ±150mV across the SENSE inputs. |
| 10 | PGND | power_in | High-current ground reference for the synchronous switch, whose return path must not corrupt SGND. |
| 11 | BG | output | Synchronous switch gate drive output. |
| 12 | VCC | power_out | Internal regulator output powering most IC functions, decoupled with a low ESR 1μF capacitor to PGND; driving it externally reduces VIN pin current to 20μA. |
| 13 | NC | unconnected | No connection. |
| 14 | SW | passive | Reference for the VBOOST supply and high-current return for the bootstrapped switch. |
| 15 | TG | output | Bootstrapped switch gate drive output. |
| 16 | BOOST | power_in | Bootstrapped supply with maximum operating voltage up to 75V (ground referred), decoupled with a low ESR 1μF capacitor to SW. |
| 17 | SGND | power_in | Exposed package backside low-noise ground reference that must be soldered to the PCB ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16-EP |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Pin (VIN) voltage | VIN | -0.3 | 65 | V | 2 | ||
| Boosted Supply Pin (BOOST) voltage | BOOST | -0.3 | 80 | V | 2 | ||
| Boosted Supply Voltage (BOOST, SW) | -0.3 | 24 | V | 2 | |||
| Boosted Supply Reference Pin (SW) voltage | SW | -2 | 65 | V | 2 | ||
| Local Supply Pin (VCC) voltage | VCC | -0.3 | 24 | V | 2 | ||
| Input voltage SENSE+, SENSE- | SENSE+, SENSE- | -0.3 | 40 | V | 2 | ||
| Input voltage SENSE+, SENSE- | SENSE+, SENSE- | -1 | 1 | V | 2 | ||
| BURST_EN pin voltage | BURST_EN | -0.3 | 24 | V | 2 | ||
| Other inputs (SHDN, CSS, VFB, VC) voltage | SHDN, CSS, VFB, VC | -0.3 | 5 | V | 2 | ||
| Input current SHDN, CSS | SHDN, CSS | -1 | 1 | mA | 2 | ||
| Operating Junction Temperature Range LT3800E | TJ | -40 | 125 | °C | Note 3 | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature (Soldering) | 300 | °C | 10 sec soldering | 2 | |||
| Maximum Junction Temperature TJMAX | TJMAX | 125 | °C | 2 | |||
| VIN Operating Voltage Range | VIN | 4 | V | Note 4 | 2 | ||
| VIN UVLO Threshold (Falling) | 3.65 | 3.8 | 3.95 | V | 2 | ||
| VBOOST Operating Voltage Range | VBOOST, VSW | 5 | V | Note 5 | 2 | ||
| VCC Output Voltage | VCC | 8 | 8.3 | V | ● | 3 | |
| VSHDN Enable Threshold (Rising) | VSHDN | 1.3 | 1.35 | 1.4 | V | 3 | |
| VSENSE Common Mode Range | VSENSE(CM) | 0 | 36 | V | 3 | ||
| Current Limit Sense Voltage | VSENSE+, VSENSE- | 140 | 150 | 175 | mV | 3 | |
| Operating Frequency | fO | 190 | 200 | 210 | kHz | 3 | |
| Operating Frequency (full temperature range) | fO | 175 | 220 | kHz | ● | 3 | |
| VFB Error Amp Reference Voltage | VFB | 1.224 | 1.231 | 1.238 | V | Measured at VFB Pin | 3 |
| VFB Error Amp Reference Voltage (full temperature range) | VFB | 1.215 | 1.245 | V | ● | 3 | |
| Error Amp Transconductance | gm | 275 | 350 | 400 | μmhos | ● | 3 |
| Error Amp Output Sink/Source Current | IVC | -30 | 30 | μA | 3 | ||
| Gate Drive Output On Voltage (Note 7) | VTG,BG | 9.8 | V | 3 | |||
| Gate Drive Output Off Voltage | VTG,BG | 0.1 | V | 3 | |||
| Minimum On Time | tTG(ON) | 300 | 500 | ns | ● | 3 | |
| VCC Burst Mode Current / Shutdown VIN supply current (VSHDN = 0V) | IVIN | 8 | 15 | μA | VSHDN = 0V | 2 | |
| Threshold Hysteresis (SHDN) | 120 | mV | 3 | ||||
| Reverse Protect Sense Voltage | VSENSE+, VSENSE- | -150 | mV | VBURST_EN = VCC | 3 | ||
| Reverse Current Offset | 10 | mV | VBURST_EN = 0V or VBURST_EN = VFB | 3 | |||
| ISENSE Input Current (ISENSE+ + ISENSE-) | 0.8 | mA | VSENSE(CM) = 0V | 3 | |||
| ISENSE Input Current (ISENSE+ + ISENSE-) | -20 | μA | VSENSE(CM) = 2.75V | 3 | |||
| ISENSE Input Current (ISENSE+ + ISENSE-) | -0.3 | mA | VSENSE(CM) > 4V | 3 | |||
| Feedback Input Current | IFB | 25 | nA | 3 | |||
| Soft-Start Disable Voltage | VFB(SS) | 1.185 | V | VFB Rising | 3 | ||
| Soft-Start Disable Hysteresis | 300 | mV | 3 | ||||
| Soft-Start Capacitor Control Current | ICSS | 2 | μA | 3 | |||
| Error Amp DC Voltage Gain | AV | 62 | dB | 3 | |||
| Gate Drive Rise/Fall Time | tTG,BG | 50 | ns | 10% to 90% or 90% to 10% | 3 | ||
| Minimum Off Time | tTG(OFF) | 450 | ns | 3 | |||
| Gate Drive Nonoverlap Time (TG Fall to BG Rise) | tNOL | 200 | ns | TG Fall to BG Rise | 3 | ||
| Gate Drive Nonoverlap Time (BG Fall to TG Rise) | tNOL | 150 | ns | BG Fall to TG Rise | 3 | ||
| Thermal Resistance Junction-to-Ambient | θJA | 40 | °C/W | 2 | |||
| Thermal Resistance Junction-to-Case | θJC | 10 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LT3800EFE#PBF - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lt3800efe-pbf-etched.step/lt3800efe-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3800efe-pbf.step/lt3800efe-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
134d0bbf44315206, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).