TPS54360DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	power_out	Bootstrap capacitor node for the high-side MOSFET gate drive. A bootstrap capacitor is required between BOOT and SW; if the BOOT-SW voltage falls below the minimum required to drive the high-side MOSFET, the output is switched off until the capacitor is refreshed (BOOT-SW absolute max 8 V).
2	VIN	power_in	Input supply voltage. Operating range 4.5 V to 60 V (absolute max 65 V). Decouple with a low-ESR ceramic capacitor close to the pin.
3	EN	input	Enable input with internal pull-up current source (~1.2 µA typ). Pull below 1.2 V to disable, float to enable. Two external resistors can program the input UVLO threshold and hysteresis. Absolute max 8.4 V.
4	RT/CLK	bidirectional	Resistor timing / external clock input. In RT mode an internal amplifier holds this pin at a fixed voltage and an external resistor to GND sets fSW (100 kHz-2.5 MHz). When pulled above the PLL upper threshold (~2 V), the pin switches to CLK mode as a synchronization input to the internal PLL; if clocking stops, the device returns to RT mode.
5	FB	input	Inverting input of the transconductance (gm) error amplifier. Regulated to the internal 0.8 V (±1%) reference by an external resistor divider from VOUT.
6	COMP	output	Error amplifier output and input to the output switch current (PWM) comparator. Connect the frequency compensation network (R+C, plus optional pole cap) to this pin.
7	GND	power_in	Device ground return. Must be tied to the exposed thermal pad on the PCB for proper operation.
8	SW	power_out	Switching node: source of the internal high-side power MOSFET. Connects to the external inductor and to the low-side catch diode/BOOT capacitor return. Absolute max −0.6 V to 65 V (−2 V for 10 ns transients).
9	Thermal Pad	passive	Exposed thermal PowerPAD on the underside of the HSOIC package. Must be electrically connected to GND on the PCB and to a copper thermal plane for proper thermal and electrical operation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

TPS54360DDAR

CAD (KiCad official)

Symbol: TPS54360DDAR
Footprint: Package_SO:TI_SO-PowerPAD-8
3D model: SOIC-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tps54360ddar.step`	123 KB	You want the bare part, or you mark your own boards.
`tps54360ddar-etched.step`	2.6 MB	You want the part with `TPS54360DDAR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 634 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 8c7b9eff00b5293a, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF