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TLV2252IDR

Public Made by Adom

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TLV2252IDR

Texas Instruments · Operational Amplifier · SOIC-8

TLV2252IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of amplifier 1, which swings rail-to-rail in single- or split-supply operation.
2 1IN− input Inverting input of amplifier 1; the common-mode input range includes the negative rail.
3 1IN+ input Non-inverting input of amplifier 1; the common-mode input range includes the negative rail.
4 VDD−/GND power_in Negative supply rail, or ground in single-supply operation; the part operates from 2.7 V to 8 V total supply.
5 2IN+ input Non-inverting input of amplifier 2; the common-mode input range includes the negative rail.
6 2IN− input Inverting input of amplifier 2; the common-mode input range includes the negative rail.
7 2OUT output Output of amplifier 2, which swings rail-to-rail in single- or split-supply operation.
8 VDD+ power_in Positive supply rail; the part operates from 2.7 V to 8 V total supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 2.7 8 V 5
Operating free-air temperature TA -40 125 °C I suffix 5
Supply voltage VDD 16 V see Note 1 5
Input current (each input) II -5 5 mA each input 5
Output current IO -50 50 mA 5
Total current into VDD+ -50 50 mA 5
Total current out of VDD− -50 50 mA 5
Operating free-air temperature range TA -40 125 °C I suffix 5
Storage temperature range Tstg -65 150 °C 5
Continuous total power dissipation PD 725 mW D-8 package, TA ≤ 25°C 5
Power dissipation derating factor 5.8 mW/°C D-8 package, above TA = 25°C 5
Input offset voltage VIO 200 1500 µV VDD = 3 V, 25°C 6
Input offset voltage VIO 1750 µV VDD = 3 V, full range (−40°C to 125°C) 6
Input offset voltage VIO 200 1500 µV VDD = 5 V, 25°C 8
Input offset voltage VIO 1750 µV VDD = 5 V, full range (−40°C to 125°C) 8
Temperature coefficient of input offset voltage αVIO 0.5 µV/°C VDD = 3 V, 25°C to 85°C 6
Input offset current IIO 0.5 60 pA VDD± = ±1.5 V, VO = 0, VIC = 0, RS = 50 Ω, 25°C 6
Input offset current IIO 1000 pA full range (−40°C to 125°C) 6
Input bias current IIB 1 60 pA VDD± = ±1.5 V, 25°C 6
Input bias current IIB 1000 pA full range (−40°C to 125°C) 6
Common-mode rejection ratio CMRR 65 75 dB VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω, 25°C, VDD = 3 V 6
Common-mode rejection ratio CMRR 60 dB VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω, full range, VDD = 3 V 6
Common-mode rejection ratio CMRR 70 83 dB VIC = 0 to 2.7 V, VO = 2.5 V, 25°C, VDD = 5 V 8
Common-mode rejection ratio CMRR 70 dB VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω, full range, VDD = 5 V 8
Supply voltage rejection ratio kSVR 80 95 dB VDD = 2.7 V to 8 V, VO = VDD/2, no load, 25°C, VDD = 3 V 7
Supply voltage rejection ratio kSVR 80 dB VDD = 2.7 V to 8 V, VIC = VDD/2, no load, full range 7
Supply voltage rejection ratio kSVR 80 95 dB VDD = 4.4 V to 8 V, VIC = VDD/2, no load, 25°C, VDD = 5 V 9
Supply current IDD 68 125 µA VO = 1.5 V, no load, 25°C, VDD = 3 V 7
Supply current IDD 150 µA VO = 1.5 V, no load, full range, VDD = 3 V 7
Supply current IDD 70 125 µA VO = 2.5 V, no load, 25°C, VDD = 5 V 9
Supply current IDD 150 µA VO = 2.5 V, no load, full range, VDD = 5 V 9
High-level output voltage VOH 2.98 V IOH = −20 µA, 25°C, VDD = 3 V 6
High-level output voltage VOH 2.9 V IOH = −75 µA, 25°C, VDD = 3 V 6
High-level output voltage VOH 2.8 V IOH = −75 µA, full range, VDD = 3 V 6
High-level output voltage VOH 4.98 V IOH = −20 µA, 25°C, VDD = 5 V 8
High-level output voltage VOH 4.9 4.94 V IOH = −75 µA, 25°C, VDD = 5 V 8
High-level output voltage VOH 4.8 V IOH = −75 µA, full range, VDD = 5 V 8
Low-level output voltage VOL 0.09 0.15 V VIC = 2.5 V, IOL = 500 µA, 25°C, VDD = 5 V 8
Low-level output voltage VOL 0.15 V VIC = 2.5 V, IOL = 500 µA, full range, VDD = 5 V 8
Large-signal differential voltage amplification AVD 100 250 V/mV VIC = 1.5 V, RL = 100 kΩ, 25°C, VDD = 3 V 6
Large-signal differential voltage amplification AVD 10 V/mV VIC = 1.5 V, VO = 1 V to 2 V, RL = 100 kΩ, full range, VDD = 3 V 6
Large-signal differential voltage amplification AVD 100 350 V/mV VIC = 2.5 V, RL = 100 kΩ, 25°C, VDD = 5 V 8
Large-signal differential voltage amplification AVD 10 V/mV VIC = 2.5 V, VO = 1 V to 4 V, RL = 100 kΩ, full range, VDD = 5 V 8
Equivalent input noise voltage Vn 19 nV/√Hz f = 1 kHz, 25°C, VDD = 3 V 7
Gain-bandwidth product 0.187 MHz f = 1 kHz, RL = 50 kΩ, CL = 100 pF, 25°C, VDD = 3 V 7
Gain-bandwidth product 0.2 MHz f = 50 kHz, RL = 50 kΩ, CL = 100 pF, 25°C, VDD = 5 V 9
Phase margin at unity gain φm 63 ° RL = 50 kΩ, CL = 100 pF, 25°C 7
Gain margin 15 dB RL = 50 kΩ, CL = 100 pF, 25°C 7

CAD (KiCad official)

  • Symbol: TLV2252IDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlv2252idr-etched.step / tlv2252idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2252idr.step / tlv2252idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 a5c7a800173131a7, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF