component
TMS320F28054FPNT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28054FPNT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
TMS320F28054FPNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S | bidirectional | General-purpose I/O 22 (default at reset), with alternate functions EQEP1S (I/O), SCITXDB (out); pullup state at reset is not stated for this pin. |
| 2 | GPIO32/SDAA | bidirectional | General-purpose I/O 32 with alternate functions SDAA (I2C data, open-drain), EPWMSYNCI (in) and EQEP1S (I/O). |
| 3 | GPIO33/SCLA | bidirectional | General-purpose I/O 33 with alternate functions SCLA (I2C clock, open-drain), EPWMSYNCO (out) and EQEP1I (I/O). |
| 4 | GPIO24/ECAP1 | bidirectional | General-purpose I/O 24 with internal pullup enabled by default; alternate functions ECAP1 (I/O) and EPWM7A (out). |
| 5 | GPIO42 | bidirectional | General-purpose I/O 42 with internal pullup enabled by default; alternate functions EPWM7B (out), SCITXDC (out) and CTRIPM1OUT (out). |
| 6 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |
| 7 | VSS | power_in | Digital ground pin. |
| 8 | XRS | bidirectional | Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor should be placed between XRS and VDDIO, and any capacitor to VSS should be 100 nF or smaller. |
| 9 | TRST | input | JTAG test reset with internal pulldown; must be maintained low during normal device operation and an external pulldown resistor is required (2.2 kΩ generally offers adequate protection). |
| 10 | ADCINA5 | input | ADC Group A, channel 5 input. |
| 11 | ADCINA4 | input | ADC Group A, channel 4 input. |
| 12 | ADCINA3 (op-amp) | input | ADC Group A, channel 3 input (labelled op-amp channel in the datasheet). |
| 13 | ADCINA2 | input | ADC Group A, channel 2 input. |
| 14 | ADCINA1 (op-amp) | input | ADC Group A, channel 1 input (labelled op-amp channel in the datasheet). |
| 15 | M1GND | power_in | Ground pin for amplifier channels A1, A3 and B1. |
| 16 | ADCINB2 | input | ADC Group B, channel 2 input. |
| 17 | ADCINB1 (op-amp) | input | ADC Group B, channel 1 input (labelled op-amp channel in the datasheet). |
| 18 | ADCINA0/VREFOUT | input | ADC Group A, channel 0 input; this pin is also the voltage reference output (VREFOUT) from the buffered DAC. |
| 19 | VREFHI | input | ADC external reference, used when in ADC external reference mode and as the reference for VREFOUT. |
| 20 | VDDA | power_in | Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin. |
| 21 | VSSA | power_in | Analog ground pin. |
| 22 | VREFLO | power_in | ADC low reference; always tied to ground. |
| 23 | ADCINA6 (op-amp) | input | ADC Group A, channel 6 input (labelled op-amp channel in the datasheet). |
| 24 | ADCINA7 | input | ADC Group A, channel 7 input. |
| 25 | ADCINB3 | input | ADC Group B, channel 3 input. |
| 26 | ADCINB4 (op-amp) | input | ADC Group B, channel 4 input (labelled op-amp channel in the datasheet). |
| 27 | M2GND | power_in | Ground pin for amplifier channels A6, B4 and B6. |
| 28 | ADCINB5 | input | ADC Group B, channel 5 input. |
| 29 | ADCINB6 (op-amp) | input | ADC Group B, channel 6 input (labelled op-amp channel in the datasheet). |
| 30 | ADCINB0 | input | ADC Group B, channel 0 input. |
| 31 | ADCINB7 (op-amp) | input | ADC Group B, channel 7 input (labelled op-amp channel in the datasheet). |
| 32 | PFCGND | power_in | Ground pin for amplifier channel B7. |
| 33 | GPIO27/SCITXDC | bidirectional | General-purpose I/O 27 with alternate function SCITXDC (SCI-C transmit data, out). |
| 34 | GPIO31/CANTXA | bidirectional | General-purpose I/O 31 with internal pullup enabled by default; alternate functions CANTXA (CAN transmit, out), SCITXDB (out) and EPWM7B (out). |
| 35 | GPIO30/CANRXA | bidirectional | General-purpose I/O 30 with internal pullup enabled by default; alternate functions CANRXA (CAN receive, in), SCIRXDB (in) and EPWM7A (out). |
| 36 | GPIO9/EPWM5B | bidirectional | General-purpose I/O 9 with alternate functions EPWM5B (out) and SCITXDB (out). |
| 37 | VSS | power_in | Digital ground pin. |
| 38 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |
| 39 | TEST2 | bidirectional | Test pin reserved for TI; must be left unconnected. |
| 40 | GPIO26 | bidirectional | General-purpose I/O 26 with alternate function SCIRXDC (SCI-C receive data, in). |
| 41 | GPIO29/SCITXDA/SCLA | bidirectional | General-purpose I/O 29 with alternate functions SCITXDA (out), SCLA (I2C clock, open-drain), TZ3 (in) and CTRIPPFCOUT (out). |
| 42 | GPIO28/SCIRXDA/SDAA | bidirectional | General-purpose I/O 28 with alternate functions SCIRXDA (SCI-A receive, in), SDAA (I2C data, open-drain) and TZ2 (in). |
| 43 | GPIO18 | bidirectional | General-purpose I/O 18 with alternate functions SPICLKA (I/O), SCITXDB (out) and XCLKOUT (output clock derived from SYSCLKOUT, reset value SYSCLKOUT/4); XCLKOUT reaches the pin only when the GPIO18 mux is set to XCLKOUT. |
| 44 | GPIO17/SPISOMIA | bidirectional | General-purpose I/O 17 with alternate functions SPISOMIA (I/O), EQEP1I (I/O), TZ3 (in) and CTRIPPFCOUT (out). |
| 45 | GPIO8/EPWM5A | bidirectional | General-purpose I/O 8 with alternate functions EPWM5A (out) and ADCSOCAO (out). |
| 46 | GPIO25 | bidirectional | General-purpose I/O 25; no peripheral alternate functions are listed for this pin. |
| 47 | GPIO16/SPISIMOA | bidirectional | General-purpose I/O 16 with alternate functions SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (in). |
| 48 | GPIO12 | bidirectional | General-purpose I/O 12 with alternate functions TZ1 (trip zone input 1, in), CTRIPM1OUT (out) and SCITXDA (out). |
| 49 | GPIO7/EPWM4B | bidirectional | General-purpose I/O 7 with alternate functions EPWM4B (out) and SCIRXDA (in). |
| 50 | GPIO6/EPWM4A | bidirectional | General-purpose I/O 6 with alternate functions EPWM4A (out), EPWMSYNCI (in) and EPWMSYNCO (out). |
| 51 | X2 | output | On-chip crystal-oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used. |
| 52 | X1 | input | On-chip 1.8-V crystal-oscillator input; a crystal or resonator connects across X1 and X2, and the pin must be tied to GND if the oscillator is not used. |
| 53 | VSS | power_in | Digital ground pin. |
| 54 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |
| 55 | GPIO19/XCLKIN | bidirectional | General-purpose I/O 19 with alternate functions XCLKIN (external oscillator input, 3.3 V oscillator), SPISTEA (I/O), SCIRXDB (in) and ECAP1 (I/O); may glitch during power-up when the on-chip VREG is used. |
| 56 | GPIO39/SCIRXDC | bidirectional | General-purpose I/O 39 with alternate functions SCIRXDC (SCI-C receive, in) and CTRIPPFCOUT (out). |
| 57 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38 with internal pullup on the JTAG function; default XCLKIN selection and TCK (JTAG test clock with internal pullup); may glitch during power-up when the on-chip VREG is used. |
| 58 | GPIO37/TDO | bidirectional | General-purpose I/O 37 and JTAG scan data output TDO (8 mA drive), shifted out on the falling edge of TCK; may glitch during power-up when the on-chip VREG is used. |
| 59 | GPIO35/TDI | bidirectional | General-purpose I/O 35 and JTAG test data input TDI with internal pullup, clocked in on the rising edge of TCK; may glitch during power-up when the on-chip VREG is used. |
| 60 | GPIO36/TMS | bidirectional | General-purpose I/O 36 and JTAG test-mode select TMS with internal pullup, clocked into the TAP controller on the rising edge of TCK; may glitch during power-up when the on-chip VREG is used. |
| 61 | GPIO11/EPWM6B | bidirectional | General-purpose I/O 11 with alternate functions EPWM6B (out), SCIRXDB (in) and reserved. |
| 62 | GPIO5/EPWM3B | bidirectional | General-purpose I/O 5 with alternate functions EPWM3B (out), SPISIMOA (I/O) and ECAP1 (I/O). |
| 63 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with alternate function EPWM3A (out). |
| 64 | GPIO40/EPWM7A | bidirectional | General-purpose I/O 40 with internal pullup enabled by default; alternate function EPWM7A (out). |
| 65 | GPIO10/EPWM6A | bidirectional | General-purpose I/O 10 with alternate functions EPWM6A (out) and ADCSOCBO (out). |
| 66 | GPIO3/EPWM2B | bidirectional | General-purpose I/O 3 with alternate functions EPWM2B (out) and SPISOMIA (I/O). |
| 67 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with alternate function EPWM2A (out). |
| 68 | GPIO1/EPWM1B | bidirectional | General-purpose I/O 1 with alternate functions EPWM1B (out) and CTRIPM1OUT (out). |
| 69 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with alternate function EPWM1A (out). |
| 70 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |
| 71 | VREGENZ | input | Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply. |
| 72 | VSS | power_in | Digital ground pin. |
| 73 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |
| 74 | GPIO34/CTRIPPFCOUT | bidirectional | General-purpose I/O 34 with alternate function CTRIPPFCOUT (out); may glitch during power-up when the on-chip VREG is used. |
| 75 | GPIO15/TZ1 | bidirectional | General-purpose I/O 15 with alternate functions TZ1 (in), CTRIPM1OUT (out) and SCIRXDB (in). |
| 76 | GPIO13/TZ2 | bidirectional | General-purpose I/O 13 with alternate function TZ2 (trip zone input 2, in). |
| 77 | GPIO14/TZ3 | bidirectional | General-purpose I/O 14 with alternate functions TZ3 (in), CTRIPPFCOUT (out) and SCITXDB (out). |
| 78 | GPIO20/EQEP1A | bidirectional | General-purpose I/O 20 with internal pullup enabled by default; alternate functions EQEP1A (in), EPWM7A (out) and CTRIPM1OUT (out). |
| 79 | GPIO21/EQEP1B | bidirectional | General-purpose I/O 21 with internal pullup enabled by default; alternate functions EQEP1B (in) and EPWM7B (out). |
| 80 | GPIO23/EQEP1I | bidirectional | General-purpose I/O 23 with alternate functions EQEP1I (I/O) and SCIRXDB (in). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
TMS320F28054FPNT - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
tms320f28054fpnt-etched.step/tms320f28054fpnt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28054fpnt.step/tms320f28054fpnt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (159 pp, sha256
aaaaedb6c548633c, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).