CD4052BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Y0	bidirectional	Y-bank channel 0 analog in/out. Connected to Y COM (pin 3) when A=0, B=0 and INH=0.
2	Y2	bidirectional	Y-bank channel 2 analog in/out. Connected to Y COM (pin 3) when A=0, B=1 and INH=0.
3	Y_COM	bidirectional	Y-bank common in/out. Bidirectional analog port that connects to one of Y0..Y3 selected by A, B when INH is low.
4	Y3	bidirectional	Y-bank channel 3 analog in/out. Connected to Y COM (pin 3) when A=1, B=1 and INH=0.
5	Y1	bidirectional	Y-bank channel 1 analog in/out. Connected to Y COM (pin 3) when A=1, B=0 and INH=0.
6	INH	input	Active-high inhibit. When INH=high, all channel switches (X and Y banks) are OFF, isolating both COM pins from all channels.
7	VEE	power_in	Negative analog supply input. Sets the lower limit of the analog signal range; must satisfy VEE ≤ VSS ≤ VDD, with (VDD - VEE) ≤ 20 V.
8	VSS	power_in	Ground / digital supply return. Reference for logic inputs A, B, INH.
9	B	input	Channel-select bit B (MSB of the 2-bit channel address). Logic input referenced to VSS; combined with A to select one of four channels per bank when INH=0.
10	A	input	Channel-select bit A (LSB of the 2-bit channel address). Logic input referenced to VSS; combined with B to select one of four channels per bank when INH=0.
11	X3	bidirectional	X-bank channel 3 analog in/out. Connected to X COM (pin 13) when A=1, B=1 and INH=0.
12	X0	bidirectional	X-bank channel 0 analog in/out. Connected to X COM (pin 13) when A=0, B=0 and INH=0.
13	X_COM	bidirectional	X-bank common in/out. Bidirectional analog port that connects to one of X0..X3 selected by A, B when INH is low.
14	X1	bidirectional	X-bank channel 1 analog in/out. Connected to X COM (pin 13) when A=1, B=0 and INH=0.
15	X2	bidirectional	X-bank channel 2 analog in/out. Connected to X COM (pin 13) when A=0, B=1 and INH=0.
16	VDD	power_in	Positive supply input. 3 V to 20 V single-supply (performance degrades below 3 V); sets the upper analog and logic-high rail. (VDD - VEE) ≤ 20 V absolute max.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Interface
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4052BPWR
CD4052BPWRE
CD4052BPWRJ
CD4052BPWRM
CD4052BPWRD
CD4052BPWRNS

CAD (KiCad official)

Symbol: CD4052BPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4052bpwr.step`	205 KB	You want the bare part, or you mark your own boards.
`cd4052bpwr-etched.step`	2.6 MB	You want the part with `CD4052BPWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 643 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (39 pp, sha256 c79b83bef7606fe6, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF