component
TPS564242DRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS564242DRLR
Texas Instruments · DC-DC Converters · SOT-563
TPS564242DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply pin, with a recommended input range of 3 V to 16 V and an absolute maximum of 18 V. |
| 2 | SW | output | Switch node connection between the high-side NFET and low-side NFET, with a recommended range of -1 V to 16 V (-6 V to 18 V for under 20 ns). |
| 3 | GND | power_in | Ground pin for the source of the low-side power NFET and the ground terminal for the controller circuit; connect together with AGND for optimal thermal performance. |
| 4 | AGND | power_in | Ground of the internal analog circuitry, to be connected to the GND plane, with a recommended range of -0.1 V to 0.1 V. |
| 5 | EN | input | Enable input to the converter; driving EN high enables the converter, with a recommended range of -0.1 V to 5.5 V. |
| 6 | FB | input | Converter feedback input, connected to the output voltage through a feedback resistor divider, with a recommended range of -0.1 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | -0.3 | 18 | V | 4 | ||
| Input voltage (FB, EN) | FB, EN | -0.3 | 6 | V | 4 | ||
| Ground voltage | AGND, PGND | -0.3 | 0.3 | V | 4 | ||
| Output voltage | SW | -2 | 18 | V | 4 | ||
| Output voltage (< 20 ns) | SW (< 20 ns) | -6.5 | 20 | V | < 20 ns | 4 | |
| Operating junction temperature range | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage | VIN | 3 | 16 | V | 4 | ||
| Input voltage (FB, EN) | FB, EN | -0.1 | 5.5 | V | 4 | ||
| Ground voltage | AGND, PGND | -0.1 | 0.1 | V | 4 | ||
| Output voltage | SW | -1 | 16 | V | 4 | ||
| Output voltage (< 20 ns) | SW (< 20 ns) | -6 | 18 | V | 4 | ||
| Output current | IO | 0 | 6 | A | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 131.1 | °C/W | 4 | |||
| Junction-to-ambient thermal resistance on EVM board | RθJA_effective | 58 | °C/W | Tested on TPS564242EVM (2-layer, 2 oz copper), VIN = 12 V, VOUT = 5 V, IOUT = 4 A, TA = 25°C | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 45.6 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 16.4 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ΨJT | 0.8 | °C/W | 4 | |||
| Junction-to-board characterization parameter | YJB | 16.1 | °C/W | 4 | |||
| VIN input voltage range | VIN | 3 | 16 | V | VIN | 5 | |
| UVLO wake-up VIN voltage | UVLO | 2.75 | 2.92 | 3 | V | Wake-up VIN voltage | 5 |
| UVLO shutdown VIN voltage | UVLO | 2.6 | 2.72 | 2.9 | V | Shutdown VIN voltage | 5 |
| FB voltage (VREF) | VREF | 594 | 600 | 606 | mV | TJ = 25°C | 5 |
| FB voltage (VREF) | VREF | 591 | 600 | 609 | mV | TJ = -40°C to 125°C | 5 |
| Overcurrent threshold | IOCL_LS | 4.5 | 6 | 7.5 | A | Valley current setpoint | 5 |
| Negative overcurrent threshold | INOCL | 1.5 | 2.5 | 3.5 | A | 5 | |
| EN threshold high level | VEN(ON) | 1.07 | 1.18 | 1.33 | V | 5 | |
| EN threshold low level | VEN(OFF) | 0.95 | 1 | 1.2 | V | 5 | |
| OVP trip threshold | VOVP | 115 | 120 | 125 | % | 5 | |
| UVP trip threshold | VUVP | 55 | 60 | 65 | % | 5 |
CAD (KiCad official)
- Symbol:
TPS564242DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps564242drlr-etched.step/tps564242drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps564242drlr.step/tps564242drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
cd59523a03e670fd, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).