component
AP1538SG-13
Public Made by Adomby adom
Diodes Incorporated DC-DC Converters, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAP1538SG-13
Diodes Incorporated · DC-DC Converters · SOIC-8
AP1538SG-13 from Diodes Incorporated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin. Connect to the resistor divider from VOUT to set the regulated output voltage using VOUT = VFB x (1 + RA/RB), with VFB typically 0.8V. |
| 2 | EN | input | Enable (power-off) pin. Drive High (>=2.0V) for normal step-down operation; drive Low (<=0.8V) to stop step-down operation and deactivate all internal circuits. |
| 3 | OCSET | input | Over-current set pin. Connect an external resistor (typically ~3kΩ) to set the maximum output current limit; internal bias current ~90µA. |
| 4 | VCC | power_in | IC power supply input. Operating range 3.6V to 18V; bypass locally with a decoupling capacitor (0.1µF typ) plus bulk input cap (e.g. 470µF). |
| 5 | Output | output | Switch node output (drain of the internal P-channel power MOSFET). Connect the external inductor and freewheel Schottky diode here; minimize trace area to reduce EMI. Pin 5 is tied internally to pin 6. |
| 6 | Output | output | Switch node output (drain of the internal P-channel power MOSFET). Connect the external inductor and freewheel Schottky diode here; minimize trace area to reduce EMI. Pin 6 is tied internally to pin 5. |
| 7 | Vss | power_in | Ground return. Pin 7 is tied internally to pin 8 and should be connected to the system ground plane. |
| 8 | Vss | power_in | Ground return. Pin 8 is tied internally to pin 7 and should be connected to the system ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
AP1538SG-13AP1538SG-13SDPG-13
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage | VFB | 0.784 | 0.8 | 0.816 | V | IOUT = 0.1A | 4 |
| Feedback Bias Current | IFB | 0.1 | 0.5 | µA | IOUT = 0.1A | 4 | |
| Line Regulation | ΔVOUT/ΔVIN | 1 | 2 | % | VIN = 5V~18V | 4 | |
| Load Regulation | ΔVOUT/VOUT | 0.2 | 0.5 | % | IOUT = 0.1 to 3A | 4 | |
| Oscillation Frequency | fOSC | 240 | 300 | 400 | KHz | Measure waveform at SW pin | 4 |
| EN Pin Input Voltage (high) | VIH | 2 | V | Evaluate oscillation at SW pin | 4 | ||
| EN Pin Input Voltage (low) | VIL | 0.8 | V | Evaluate oscillation stop at SW pin | 4 | ||
| OCSET Pin Bias Current | IOCSET | 75 | 90 | 105 | µA | 4 | |
| Input Voltage | VIN | 3.6 | 18 | V | Note 5 | 3 | |
| Output Current | IOUT | 0 | 3 | A | 3 | ||
| Operating Ambient Temperature | TA | -20 | 85 | °C | 3 | ||
| Human Body Model ESD Protection | ESD HBM | 5.5 | KV | 3 | |||
| Machine Model ESD Protection | ESD MM | 200 | V | 3 | |||
| VCC Pin Voltage | VCC | -0.3 | 20 | V | Relative to VSS (printed as VSS - 0.3 to VSS + 20) | 3 | |
| Feedback Pin Voltage | VFB | -0.3 | V | Relative to VSS; upper limit printed as VCC | 3 | ||
| EN Pin Voltage | VEN | -0.3 | V | Relative to VSS; upper limit printed as VCC | 3 | ||
| Switch Pin Voltage | VOUT | -0.3 | V | Relative to VSS; upper limit printed as VCC | 3 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Storage Temperature Range | TST | -65 | 150 | °C | 3 | ||
| Thermal Resistance Junction-to-Case, SOP-8L | θJC | 24 | °C/W | Note 6: 2oz copper, minimum recommended pad layout top & bottom, thermal vias, double-sided FR-4 PCB | 4 |
CAD (KiCad official)
- Symbol:
AP1538SG-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ap1538sg-13-etched.step/ap1538sg-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap1538sg-13.step/ap1538sg-13.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ap1538sg-13.step |
122 KB | You want the bare part, or you mark your own boards. |
ap1538sg-13-etched.step |
2.5 MB | You want the part with AP1538SG-13 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 598 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (12 pp, sha256
638a3ccf88cbfdca, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).