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AD5667RBRMZ-2
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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5667RBRMZ-2
Analog Devices · Digital To Analog Converters (DACs) · MSOP-10
AD5667RBRMZ-2 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A, driven by a rail-to-rail output amplifier with an output range of 0 V to VDD. |
| 2 | VOUTB | output | Analog output voltage from DAC B, driven by a rail-to-rail output amplifier with an output range of 0 V to VDD. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Pulsing this pin low updates any or all DAC registers that have new data, and it can alternatively be tied permanently low. |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero scale to all registers, clears the output to 0 V, and causes LDAC pulses to be ignored while low. |
| 6 | ADDR | input | Three-state address input that sets the two least significant bits (A1, A0) of the 7-bit slave address. |
| 7 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input register. |
| 8 | SDA | bidirectional | Bidirectional open-drain serial data line that must be pulled to the supply with an external pull-up resistor. |
| 9 | VDD | power_in | Power supply input operated from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 10 | VREFIN/VREFOUT | bidirectional | Reference input by default and reference output when the internal reference is used, with the internal reference available only on R suffix versions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (AD5667R) | INL | 8 | 12 | LSB | 3 | ||
| Differential Nonlinearity (AD5667R) | DNL | -1 | 1 | LSB | Guaranteed monotonic by design | 3 | |
| Zero-Code Error | 2 | 10 | mV | All 0s loaded to DAC register | 3 | ||
| Offset Error | 1 | 10 | mV | 3 | |||
| Full-Scale Error | -0.1 | 1 | % of FSR | All 1s loaded to DAC register | 3 | ||
| Gain Error | -1.5 | 1.5 | % of FSR | 3 | |||
| Zero-Code Error Drift | -2 | 2 | µV/°C | 3 | |||
| Gain Temperature Coefficient | -2.5 | 2.5 | ppm of FSR/°C | 3 | |||
| DC Crosstalk (External Reference) due to full-scale output change | 15 | µV | RL = 2 kΩ to GND or 2 kΩ to VDD | 3 | |||
| DC Crosstalk (External Reference) due to load current change | 10 | µV/mA | 3 | ||||
| DC Crosstalk (External Reference) due to powering down | 8 | µV | per channel | 3 | |||
| DC Crosstalk (Internal Reference) due to full-scale output change | 25 | µV | RL = 2 kΩ to GND or 2 kΩ to VDD | 3 | |||
| DC Crosstalk (Internal Reference) due to load current change | 20 | µV/mA | 3 | ||||
| DC Crosstalk (Internal Reference) due to powering down | 10 | µV | per channel | 3 | |||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 3 | |||
| Capacitive Load Stability | 10 | nF | RL = 2 kΩ | 3 | |||
| Reference Current | 110 | 130 | µA | VREF = VDD = 5.5 V | 3 | ||
| Reference Output Voltage (MSOP package) | 2.495 | 2.505 | V | At ambient | 3 | ||
| Reference TC (MSOP package) | 5 | 10 | ppm/°C | 3 | |||
| Logic Output Low Voltage VOL | VOL | 0.4 | V | ISINK = 3 mA | 4 | ||
| Logic Output Low Voltage VOL | VOL | 0.6 | V | ISINK = 6 mA | 4 | ||
| Floating-State Leakage Current | -1 | 1 | µA | 4 | |||
| Logic Input Current | IIN | -1 | 1 | µA | 4 | ||
| Supply Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| IDD Normal Mode, internal reference off | IDD | 0.4 | 0.5 | mA | VDD = 4.5 V to 5.5 V; VIH = VDD, VIL = GND | 4 | |
| IDD Normal Mode, internal reference off | IDD | 0.35 | 0.45 | mA | VDD = 2.7 V to 3.6 V; VIH = VDD, VIL = GND | 4 | |
| IDD Normal Mode, internal reference on | IDD | 0.95 | 1.15 | mA | VDD = 4.5 V to 5.5 V; VIH = VDD, VIL = GND | 4 | |
| IDD Normal Mode, internal reference on | IDD | 0.8 | 0.95 | mA | VDD = 2.7 V to 3.6 V; VIH = VDD, VIL = GND | 4 | |
| IDD All Power-Down Modes | IDD | 0.48 | 1 | µA | VIH = VDD, VIL = GND | 4 | |
| Operating Temperature Range, Industrial | TA | -40 | 105 | °C | 8 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 8 | ||
| Junction Temperature (TJ maximum) | TJ | 150 | °C | 8 | |||
| Thermal Impedance θJA (MSOP package) | θJA | 150.4 | °C/W | MSOP package | 8 | ||
| fSCL Serial Clock Frequency, high speed mode | fSCL | 3.4 | MHz | High speed mode, CB = 100 pF | 6 | ||
| fSCL Serial Clock Frequency, high speed mode | fSCL | 1.7 | MHz | High speed mode, CB = 400 pF | 6 | ||
| t1 tHIGH, SCL high time | t1 | 60 | ns | High speed mode, CB = 100 pF | 6 | ||
| t2 tLOW, SCL low time | t2 | 160 | ns | High speed mode, CB = 100 pF | 6 | ||
| t3 tSU;DAT, data setup time | t3 | 10 | ns | High speed mode | 6 | ||
| t4 tHD;DAT, data hold time | t4 | 0 | 70 | ns | High speed mode, CB = 100 pF | 6 | |
| t5 tSU;STA, setup time for a repeated start condition | t5 | 160 | ns | High speed mode | 6 | ||
| t6 tHD;STA, hold time (repeated) start condition | t6 | 160 | ns | High speed mode | 6 | ||
| t8 tSU;STO, setup time for a stop condition | t8 | 160 | ns | High speed mode | 6 | ||
| t9 tRDA, rise time of SDA signal | t9 | 10 | 80 | ns | High speed mode, CB = 100 pF | 6 | |
| t10 tFDA, fall time of SDA signal | t10 | 10 | 80 | ns | High speed mode, CB = 100 pF | 6 | |
| t11 tRCL, rise time of SCL signal | t11 | 10 | 40 | ns | High speed mode, CB = 100 pF | 6 | |
| t12 tFCL, fall time of SCL signal | t12 | 10 | 40 | ns | High speed mode, CB = 100 pF | 7 | |
| t14 falling edge of 9th SCL clock to LDAC falling edge | t14 | 30 | ns | High speed mode | 7 | ||
| t15 CLR pulse width low | t15 | 20 | ns | High speed mode | 7 | ||
| tSP Pulse width of spike suppressed | tSP | 0 | 10 | ns | High speed mode | 7 | |
| DC Power Supply Rejection Ratio | PSRR | -100 | dB | DAC code = midscale; VDD = 5 V ± 10% | 3 | ||
| Short-Circuit Current | ISC | 30 | mA | VDD = 5 V | 3 | ||
| Power-Up Time | 4 | µs | Coming out of power-down mode; VDD = 5 V | 3 | |||
| DC Output Impedance | 0.5 | Ω | 3 | ||||
| Reference Input Impedance | 50 | kΩ | 3 | ||||
| Reference Output Impedance (MSOP package) | 7.5 | kΩ | 3 | ||||
| Pin Capacitance ADDR | CIN | 2 | pF | ADDR | 4 | ||
| Pin Capacitance CLR, LDAC | CIN | 20 | pF | CLR, LDAC | 4 | ||
| Floating-State Output Capacitance | 2 | pF | 4 |
CAD (KiCad official)
- Symbol:
AD5667RBRMZ-2 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5667rbrmz-2-etched.step/ad5667rbrmz-2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5667rbrmz-2.step/ad5667rbrmz-2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (30 pp, sha256
dd375772240388df, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).