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CD4019BM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4019BM96
Texas Instruments · Logic Gates · SOIC-16
CD4019BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B4 | input | Channel-B data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input. |
| 2 | A3 | input | Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input. |
| 3 | B3 | input | Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input. |
| 4 | A2 | input | Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input. |
| 5 | B2 | input | Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input. |
| 6 | A1 | input | Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input. |
| 7 | B1 | input | Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input. |
| 8 | VSS | power_in | Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a −0.5 V to +20 V range. |
| 9 | Ka | input | Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range. |
| 10 | D1 | output | Select-gate 1 output, D1 = A1·Ka + B1·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |
| 11 | D2 | output | Select-gate 2 output, D2 = A2·Ka + B2·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |
| 12 | D3 | output | Select-gate 3 output, D3 = A3·Ka + B3·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |
| 13 | D4 | output | Select-gate 4 output, D4 = A4·Ka + B4·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |
| 14 | Kb | input | Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range. |
| 15 | A4 | input | Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input. |
| 16 | VDD | power_in | Positive DC supply voltage terminal, referenced to VSS, rated −0.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4019BM96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd4019bm96-etched.step/cd4019bm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4019bm96.step/cd4019bm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
97c4321a9ad89a2e, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(text+vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).