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TPS562243DRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS562243DRLR
Texas Instruments · DC-DC Converters · SOT-563
TPS562243DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply pin, rated 4.2 V to 17 V recommended (4.5 V to 17 V for TPS562246B). |
| 2 | SW | output | Switch node connection between the high-side NFET and low-side NFET; recommended operating range is -1 V to 17 V (DC). |
| 3 | GND | power_in | Ground pin, source terminal of the low-side power NFET and ground for the control circuit; connect the sensitive FB network to this GND at a single point. |
| 4 | BST | output | Supply input for the high-side NFET gate drive circuit; connect a 0.1 µF capacitor between BST and SW. |
| 5 | EN | input | Active-high enable input that must be pulled up to enable the device; recommended input range is -0.1 V to 5.5 V. |
| 6 | FB | input | Converter feedback input, connected to the output voltage through a feedback resistor divider; recommended input range is -0.1 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Input voltage range | VIN | 4.2 | 17 | V | 5 | ||
| UVLO VIN undervoltage lockout Wake up VIN voltage | UVLO | 3.6 | 3.8 | 4 | V | 5 | |
| UVLO VIN undervoltage lockout Shut down VIN voltage | UVLO | 3.2 | 3.4 | 3.6 | V | 5 | |
| FB voltage | VFB | 591 | 600 | 609 | mV | TJ = 25°C, Vin = 4.2 - 17 V | 5 |
| FB voltage | VFB | 588 | 600 | 612 | mV | TJ = -40°C to 125°C, Vin = 4.2 - 17 V | 5 |
| Over current threshold (valley current set point) | IOCL_LS | 2 | 2.8 | 3.6 | A | Valley current set point | 5 |
| Negative over current threshold (valley current set point) | INOCL | 1 | 1.8 | 2.5 | A | Valley current set point | 5 |
| EN threshold high-level | VEN(ON) | 1.15 | 1.2 | 1.28 | V | 6 | |
| EN threshold low-level | VEN(OFF) | 0.93 | 1 | 1.05 | V | 6 | |
| UVP trip threshold | VUVP | 55 | 60 | 65 | PNCT | 6 | |
| VIN Input voltage | VIN | -0.3 | 19 | V | 4 | ||
| Input voltage FB, EN | FB, EN | -0.3 | 6 | V | 4 | ||
| Input voltage GND | GND | -0.3 | 0.3 | V | 4 | ||
| Output voltage BST | BST | -0.3 | 25 | V | 4 | ||
| Output voltage BST (< 20ns) | BST | -0.3 | 27 | V | < 20ns | 4 | |
| Output voltage SW | SW | -2 | 19 | V | 4 | ||
| Output voltage SW (< 20ns) | SW | -6.5 | 21 | V | < 20ns | 4 | |
| Operating junction temperature range | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage VIN | VIN | 4.2 | 17 | V | 4 | ||
| Input voltage FB, EN | FB, EN | -0.1 | 5.5 | V | 4 | ||
| Input voltage GND | GND | -0.1 | 0.1 | V | 4 | ||
| Output voltage BST | BST | -0.1 | 23 | V | 4 | ||
| Output voltage BST (< 20ns) | BST | -0.1 | 25 | V | < 20ns | 4 | |
| Output voltage SW | SW | -1 | 17 | V | 4 | ||
| Output voltage SW (< 20ns) | SW | -6 | 19 | V | < 20ns | 4 | |
| Output Current | IO | 0 | 2 | A | 4 | ||
| TJ Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Tstg Storage temperature | Tstg | -40 | 150 | °C | 4 | ||
| VIN supply current (ECO version) | IVIN | 110 | µA | No load, VEN = 1.5 V, non-switching, ECO version | 5 | ||
| VIN shutdown current | IINSDN | 7 | µA | VEN = 0 V | 5 | ||
| UVLO VIN undervoltage lockout Hysteresis VIN voltage | UVLO | 400 | mV | 5 | |||
| High-side MOSFET Rds(on) | RDS(ON)HI | 100 | mΩ | TJ = 25°C | 5 | ||
| Low-side MOSFET Rds(on) | RDS(ON)LO | 55 | mΩ | TJ = 25°C | 5 | ||
| Switching frequency | FSW | 1280 | kHz | VOUT = 3.3 V | 5 | ||
| Minimum off-time | TOFF(MIN) | 100 | ns | VFB = 0.5 V | 5 | ||
| Minimum on-time | TON(MIN) | 55 | ns | 5 | |||
| EN hysteresis | VENHYS | 200 | mV | 6 | |||
| EN pulldown current | IEN | 1 | uA | VEN = 1.5 V | 6 | ||
| Internal soft start time | tSS | 1.4 | ms | VOUT from 0 to target value. | 6 | ||
| UVP prop deglitch | tUVPDLY | 256 | us | 6 | |||
| UVP switching time in continuous hiccup mode | tUVPON | 1.5 | ms | In continus hiccup mode, the switching time; Hard short, UVP detect | 6 | ||
| UVP non-switching time in continuous hiccup mode | tUVPOFF | 13 | ms | In continus hiccup mode, non switching time; Hard short, UVP detect | 6 | ||
| OTP trip threshold | TOTP | 155 | °C | 6 | |||
| OTP hysteresis | TOTPHSY | 20 | °C | 6 | |||
| Junction-to-ambient thermal resistance | RθJA | 147.4 | °C/W | 5 | |||
| Junction-to-ambient thermal resistance on EVM board | RθJA_effective | 73 | °C/W | Tested on TPS562243EVM board (2 layer, 2oz copper), TA = 25°C | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 75.7 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 32.2 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ΨJT | 2.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | YJB | 31.8 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS562243DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps562243drlr-etched.step/tps562243drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps562243drlr.step/tps562243drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
111a2d7e7b559d53, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).