component
TLV70450DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTLV70450DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TLV70450DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground reference. All voltages are referenced to this network ground terminal. |
| 2 | IN | power_in | Unregulated input voltage. Operating range 2.5 V to 24 V; absolute max -0.3 V to 24 V. A 0.1-µF input bypass capacitor to GND is recommended. |
| 3 | OUT | power_out | Regulated output voltage (5.0 V nominal for TLV70450). Current internally limited; rated for up to 150 mA. Requires an output capacitor greater than 1 µF between this pin and GND for stability. |
| 4 | NC | unconnected | Not internally connected. May be left open or tied to GND for improved thermal performance. |
| 5 | NC | unconnected | Not internally connected. May be left open or tied to GND for improved thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
TLV70450DBVRTLV70450DBVRDBVT
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage (IN) – absolute maximum | -0.3 | 24 | V | All voltages with respect to network ground terminal | 5 | ||
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | Over operating junction temperature range | 5 | |
| Storage temperature range | Tstg | -65 | 150 | °C | 5 | ||
| Input voltage | VIN | 2.5 | 24 | V | Over operating junction temperature range | 5 | |
| Output current | IOUT | 0 | 150 | mA | Over operating junction temperature range | 5 | |
| Operating junction temperature | TJ | -40 | 125 | °C | Over operating junction temperature range | 5 | |
| Input voltage range | VIN | 24 | V | 6 | |||
| Output voltage range | VOUT | 1.2 | 5 | V | 6 | ||
| DC output accuracy | VOUT | -2 | 2 | % | 6 | ||
| Line regulation | ΔVO(ΔVI) | 20 | 50 | mV | V(nom) + 1 V < VIN < 24 V | 6 | |
| Load regulation (VOUT ≥ 3.3 V) | ΔVO(ΔIO) | 7 | mV | VOUT ≥ 3.3 V; 0 mA < IOUT < 10 mA | 6 | ||
| Load regulation (VOUT ≥ 3.3 V) | ΔVO(ΔIO) | 35 | mV | VOUT ≥ 3.3 V; 0 mA < IOUT < 50 mA | 6 | ||
| Load regulation (VOUT ≥ 3.3 V) | ΔVO(ΔIO) | 50 | 75 | mV | VOUT ≥ 3.3 V; 0 mA < IOUT < 100 mA | 6 | |
| Dropout voltage | VDO | 75 | mV | IOUT = 10 mA; VIN = VOUT(nom) – 0.1 V | 6 | ||
| Dropout voltage | VDO | 400 | mV | IOUT = 50 mA; VIN = VOUT(nom) – 0.1 V | 6 | ||
| Dropout voltage | VDO | 850 | 1100 | mV | IOUT = 100 mA; VIN = VOUT(nom) – 0.1 V | 6 | |
| Output current limit | ICL | 160 | 1000 | mA | VOUT = 0 V | 6 | |
| Ground pin current | IGND | 3.2 | 4.5 | µA | IOUT = 0 mA | 6 | |
| Ground pin current | IGND | 3.4 | 5.5 | µA | IOUT = 100 mA | 6 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 213.1 | °C/W | DBV package (5 pins) | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 110.9 | °C/W | DBV package (5 pins) | 5 | ||
| Junction-to-board thermal resistance | RθJB | 97.4 | °C/W | DBV package (5 pins) | 5 | ||
| Junction-to-top characterization parameter | ψJT | 22 | °C/W | DBV package (5 pins) | 5 | ||
| Junction-to-board characterization parameter | ψJB | 78.4 | °C/W | DBV package (5 pins) | 5 |
CAD (KiCad official)
- Symbol:
TLV70450DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv70450dbvr-etched.step/tlv70450dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv70450dbvr.step/tlv70450dbvr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tlv70450dbvr.step |
85 KB | You want the bare part, or you mark your own boards. |
tlv70450dbvr-etched.step |
1.9 MB | You want the part with TLV70450DBVR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 483 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (22 pp, sha256
a398aa95860978a5, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).