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MSP430FR59941IRGZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR59941IRGZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
MSP430FR59941IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TA0.1, DMAE0, RTCCLK, ADC input A0, comparator input C0 and VREF-/VeREF-. |
| 2 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TA0.2, TA1CLK, COUT, ADC input A1, comparator input C1 and VREF+/VeREF+. |
| 3 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TA1.1, TA0CLK, COUT, ADC input A2 and comparator input C2. |
| 4 | P3.0/A12/C12 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A12 and comparator input C12. |
| 5 | P3.1/A13/C13 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, powered from DVCC; alternate function is ADC input A13 and comparator input C13. |
| 6 | P3.2/A14/C14 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A14 and comparator input C14. |
| 7 | P3.3/A15/C15 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A15 and comparator input C15. |
| 8 | P4.7 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC. |
| 9 | P1.3/TA1.2/UCB0STE/A3/C3 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TA1.2, UCB0STE, ADC input A3 and comparator input C3. |
| 10 | P1.4/TB0.1/UCA0STE/A4/C4 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TB0.1, UCA0STE, ADC input A4 and comparator input C4. |
| 11 | P1.5/TB0.2/UCA0CLK/A5/C5 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternates include TB0.2, UCA0CLK, ADC input A5 and comparator input C5. |
| 12 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 | bidirectional | General-purpose I/O (PJ.0) shared with JTAG TDO, TB0OUTH, SMCLK, SRSCG1 and comparator input C6; keep open when used as a JTAG pin. |
| 13 | PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 | bidirectional | General-purpose I/O (PJ.1) shared with JTAG TDI/TCLK, MCLK, SRSCG0 and comparator input C7; keep open when used as a JTAG pin. |
| 14 | PJ.2/TMS/ACLK/SROSCOFF/C8 | bidirectional | General-purpose I/O (PJ.2) shared with JTAG TMS, ACLK, SROSCOFF and comparator input C8; keep open when used as a JTAG pin. |
| 15 | PJ.3/TCK/SRCPUOFF/C9 | bidirectional | General-purpose I/O (PJ.3) shared with JTAG TCK, SRCPUOFF and comparator input C9; keep open when used as a JTAG pin. |
| 16 | P4.0/A8 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A8. |
| 17 | P4.1/A9 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A9. |
| 18 | P4.2/A10 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A10. |
| 19 | P4.3/A11 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5, reset state OFF, powered from DVCC; alternate function is ADC input A11. |
| 20 | P2.5/TB0.0/UCA1TXD/UCA1SIMO | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.0 and eUSCI_A1 transmit/SIMO. |
| 21 | P2.6/TB0.1/UCA1RXD/UCA1SOMI | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.1 and eUSCI_A1 receive/SOMI. |
| 22 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins and serves as Spy-Bi-Wire clock input; it has an internal pulldown that is always enabled, so leave it open when unused. |
| 23 | RST/NMI/SBWTDIO | input | Active-low reset input, also NMI and Spy-Bi-Wire data; if unused, connect to DVCC through a 47-kΩ pullup (or internal pullup) with 10-nF pulldown (2.2 nF maximum when using Spy-Bi-Wire or 4-wire JTAG tools). |
| 24 | P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.6, eUSCI_A0 transmit/SIMO, TB0CLK and ACLK output. |
| 25 | P2.1/TB0.0/UCA0RXD/UCA0SOMI | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.0 and eUSCI_A0 receive/SOMI. |
| 26 | P2.2/TB0.2/UCB0CLK | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.2 and eUSCI_B0 clock. |
| 27 | P3.4/TB0.3/SMCLK | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.3 and SMCLK output. |
| 28 | P3.5/TB0.4/COUT | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TB0.4 and comparator output COUT. |
| 29 | P3.6/TB0.5 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternate function is TB0.5. |
| 30 | P3.7/TB0.6 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternate function is TB0.6. |
| 31 | P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; on this I2C-BSL device it is BSLSDA, and alternates include TB0.3, eUSCI_B0 SIMO/SDA and TA0.0. |
| 32 | P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; on this I2C-BSL device it is BSLSCL, and alternates include TB0.4, eUSCI_B0 SOMI/SCL and TA1.0. |
| 33 | P4.4/TB0.5 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternate function is TB0.5 capture/compare. |
| 34 | P4.5 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5. |
| 35 | P4.6 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5. |
| 36 | DVSS1 | power_in | Digital ground supply (0 V) for the digital domain. |
| 37 | DVCC1 | power_in | Digital power supply; VCC must be 1.8 V to 3.6 V (SVS limit applies), decoupled with 1 µF plus 100 nF placed close to the pin. |
| 38 | P2.7 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; no alternate peripheral function listed. |
| 39 | P2.3/TA0.0/UCA1STE/A6/C10 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TA0.0, eUSCI_A1 STE, ADC input A6 and comparator input C10. |
| 40 | P2.4/TA1.0/UCA1CLK/A7/C11 | bidirectional | General-purpose I/O with port interrupt and wake-up from LPMx.5; alternates include TA1.0, eUSCI_A1 clock, ADC input A7 and comparator input C11. |
| 41 | AVSS3 | power_in | Analog ground supply (0 V). |
| 42 | PJ.6/HFXIN | bidirectional | Port PJ.6 shared with the high-frequency crystal oscillator input HFXIN, or the bypass clock input when HFXTBYPASS is selected. |
| 43 | PJ.7/HFXOUT | bidirectional | Port PJ.7 shared with the high-frequency crystal oscillator output HFXOUT; it becomes general-purpose I/O when HFXT bypass mode is used. |
| 44 | AVSS2 | power_in | Analog ground supply (0 V). |
| 45 | PJ.4/LFXIN | bidirectional | Port PJ.4 shared with the low-frequency (32 kHz) crystal oscillator input LFXIN, or the bypass clock input when LFXTBYPASS is selected. |
| 46 | PJ.5/LFXOUT | bidirectional | Port PJ.5 shared with the low-frequency (32 kHz) crystal oscillator output LFXOUT; it becomes general-purpose I/O when LFXT bypass mode is used. |
| 47 | AVSS1 | power_in | Analog ground supply (0 V). |
| 48 | AVCC1 | power_in | Analog power supply; VCC must be 1.8 V to 3.6 V, and the difference between DVCC and AVCC must stay within ±0.3 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
MSP430FR59941IRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
msp430fr59941irgzr-etched.step/msp430fr59941irgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr59941irgzr.step/msp430fr59941irgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (177 pp, sha256
305369231542d625, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).