component
GM1203BACPZ-2-R7
Public Made by Adomby adom
GONGMOSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownGM1203BACPZ-2-R7
GONGMOSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(5x5)
GM1203BACPZ-2-R7 from GONGMOSEMI, in a QFN-20(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor from OUT to GND, placed as close to the pin as possible, is required for stability. |
| 2 | NC | unconnected | Not connected. |
| 3 | NC | unconnected | Not connected. |
| 4 | NC | unconnected | Not connected. |
| 5 | IN | power_in | Input supply pin, operating range 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) from IN to GND placed as close to the pin as possible. |
| 6 | IN | power_in | Input supply pin, operating range 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) from IN to GND placed as close to the pin as possible. |
| 7 | IN | power_in | Input supply pin, operating range 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) from IN to GND placed as close to the pin as possible. |
| 8 | IN | power_in | Input supply pin, operating range 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) from IN to GND placed as close to the pin as possible. |
| 9 | PG | output | Active-high open-drain power-good output that goes high-impedance when the output is in regulation and is pulled to GND otherwise, requiring an external pull-up of 10 kΩ to 100 kΩ. |
| 10 | BIAS | power_in | Bias supply input that lowers power dissipation and improves DC and AC performance when VIN ≤ 2.2 V; a 10 µF or larger capacitor to GND is required, and the pin must be left floating or grounded if unused. |
| 11 | EN | input | Enable input: a high level above 1.1 V enables the device and a low level below 0.4 V disables it, and it must be tied to IN or BIAS if the enable function is not used. |
| 12 | GND | power_in | Ground pin that must have a low-impedance connection to the exposed thermal pad. |
| 13 | NC | unconnected | Not connected. |
| 14 | NC | unconnected | Not connected. |
| 15 | NR/SS | passive | Noise-reduction and soft-start pin; a capacitor to GND lowers reference noise and sets the soft-start ramp, with 10 nF or larger recommended as close to the pin as possible. |
| 16 | FB | input | Feedback pin connected to the error amplifier; a 10 nF feed-forward capacitor from FB to OUT placed close to the device is recommended for AC performance. |
| 17 | NC | unconnected | Not connected. |
| 18 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor from OUT to GND, placed as close to the pin as possible, is required for stability. |
| 19 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor from OUT to GND, placed as close to the pin as possible, is required for stability. |
| 20 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor from OUT to GND, placed as close to the pin as possible, is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GONGMOSEMI |
| Package | QFN-20(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Accuracy over line, load and temperature (0.5 V <= VOUT <= 3.65 V) | -1 | 1 | % | 0.5 V ≤ VOUT ≤ 3.65 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 9 | ||
| Accuracy with BIAS | -1 | 1.3 | % | VIN = 1.1 V, VOUT = 0.5 V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 9 | ||
| Output voltage range GM1203B, pin-programmed | VFB | 0.8 | 3.95 | V | 使用引脚编程 | 9 | |
| Output voltage range GM1203B, external resistors | VFB | 0.8 | 5.5 | V | 使用外部电阻(2) | 9 | |
| Minimum IN voltage with BIAS (UVLO) | VUVLO | 0.98 | 1.085 | V | VBIAS = 3.0 V, TJ = -40°C to +125°C | 9 | |
| Minimum IN voltage without BIAS (UVLO), VIN rising | VUVLO1 | 1.32 | 1.49 | V | TJ = -40°C to +125°C, VIN rising | 9 | |
| Minimum BIAS input voltage (UVLO), VBIAS rising | VBIAS_UVLO | 2.2 | 2.9 | V | VIN = 1.1 V, VBIAS rising | 9 | |
| Dropout voltage, IOUT = 3 A | VDO | 140 | 260 | mV | VIN = 1.5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, IOUT = 3 A, VIN = 5.4 V | VDO | 115 | 220 | mV | VIN = 5.4 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, IOUT = 3 A, VBIAS = 5 V | VDO | 120 | 210 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Output current limit (3 A variant) | ILIM | 3.7 | 4.2 | 6.7 | A | VOUT forced to 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 9 |
| EN pin low-level input voltage | VEN_IL | 0 | 0.4 | V | 9 | ||
| EN pin high-level input voltage | VEN_IH | 1.1 | 6.5 | V | 9 | ||
| EN pin current | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 9 | |
| PG falling threshold | VPG_FALLING | 82 | 91 | 93 | % × VOUT | 下降 | 9 |
| PG low-level output voltage | VPG_OL | 0.4 | V | VOUT < VPG_FALLING, IPG = -1 mA | 9 | ||
| NR/SS charging current | INR/SS | 4 | 9 | 11.5 | µA | VNR/SS = GND, VIN = 6.5 V | 10 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 10 | |
| Absolute max IN, BIAS, PG, EN to GND voltage | -0.3 | 7 | V | 8 | |||
| Absolute max SNS, OUT to GND voltage (upper limit printed as VIN+0.3 V) | -0.3 | V | 8 | ||||
| Absolute max NR/SS, FB to GND voltage | -0.3 | 3.6 | V | 8 | |||
| Absolute max VOUT-setting pins (50mV, 100mV, 200mV, 400mV, 800mV) to GND voltage (upper limit printed as VOUT+0.3 V) | -0.3 | V | 8 | ||||
| Absolute max PG current | -5 | mA | 8 | ||||
| Storage temperature range | -65 | 150 | °C | 8 | |||
| Operating temperature range (A grade) | -40 | 125 | °C | 8 | |||
| Input voltage operating range | VIN | 1.1 | 6.5 | V | 18 | ||
| BIAS supply voltage when VIN < 1.5 V | VBIAS | 3 | V | VIN < 1.5 V | 18 | ||
| Output capacitor (ceramic) | COUT | 47 | µF | ceramic; 22 µF or more effective | 18 | ||
| Input capacitor (ceramic) | CIN | 10 | µF | ceramic at IN to GND; 5 µF or more effective | 18 | ||
| BIAS pin capacitor to GND | CBIAS | 10 | µF | 7 | |||
| Continuous operating junction temperature | TJ | 125 | °C | continuous operation | 20 | ||
| Junction-to-ambient thermal resistance, 20-pin 5 mm × 5 mm QFN | θJA | 35.4 | °C/W | worst case, soldered to PCB | 8 | ||
| GND pin current, shutdown | IGND | 18 | µA | 关断, VIN = 6.5 V, VEN = 0.5 V | 9 | ||
| GND pin current, VIN = 6.5 V, IOUT = 5 mA | IGND | 15 | mA | VIN = 6.5 V, IOUT = 5 mA | 9 | ||
| GND pin current, VIN = 1.5 V, IOUT = 3 A | IGND | 15 | mA | VIN = 1.5 V, VOUT = 1.0 V, IOUT = 3 A | 9 | ||
| BIAS pin current | IBIAS | 16 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT = 0.8 V, IOUT = 3 A | 9 | ||
| UVLO hysteresis with BIAS | VUVLO_HYS | 100 | mV | VBIAS = 3.0 V | 9 | ||
| IN UVLO threshold without BIAS, VIN rising (second value) | VUVLO1 | 1.59 | V | VIN 逐渐上升 | 9 | ||
| UVLO hysteresis without BIAS | VUVLO1_HYS | 115 | mV | 9 | |||
| BIAS UVLO hysteresis | VBIAS_UVLO_HYS | 200 | mV | VIN = 1.1 V | 9 | ||
| Line regulation | ΔVOUT/ΔVIN | 0.1 | mV/V | VIN = Max(VOUT + 0.4 V, 1.5 V) to 6.5 V | 9 | ||
| Load regulation | ΔVOUT/ΔIOUT | 0.2 | mV/A | 5 mA ≤ IOUT ≤ 3 A | 9 | ||
| PG hysteresis, rising | VPG_HYS | 2 | % × VOUT | 上升 | 9 | ||
| PG leakage current | IPG_LK | 1 | µA | VOUT > VPG_FALLING + VPG_HYS, VPG = 6.5 V | 9 | ||
| NR/SS pin voltage | VNR/SS | 0.5 | V | 10 | |||
| PSRR at 10 kHz, VOUT = 0.8 V | PSRR | 68 | dB | f = 10 kHz, VOUT = 0.8 V, VBIAS = 5.0 V | 10 | ||
| PSRR at 1 MHz, VOUT = 0.8 V | PSRR | 51 | dB | f = 1 MHz, VOUT = 0.8 V, VBIAS = 5.0 V | 10 | ||
| PSRR at 10 kHz, VOUT = 5.0 V | PSRR | 58 | dB | f = 10 kHz, VOUT = 5.0 V | 10 | ||
| PSRR at 1 MHz, VOUT = 5.0 V | PSRR | 43 | dB | f = 1 MHz, VOUT = 5.0 V | 10 | ||
| Output noise, VOUT = 0.5 V or 0.8 V | VN | 3 | µVRMS | BW = 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.5 V or 0.8 V, VBIAS = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF | 10 | ||
| Output noise, VOUT = 5.0 V | VN | 14.8 | µVRMS | BW = 10 Hz to 100 kHz, VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF | 10 | ||
| Thermal shutdown threshold | TSD | 150 | °C | 关断阈值，温度不断上升 | 10 | ||
| Thermal shutdown hysteresis | TSD_HYS | 20 | °C | 开机阈值，温度不断下降 | 10 |
CAD (KiCad official)
- Symbol:
GM1203BACPZ-2-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: QFN-20(5x5) (KiCad packages3D, STEP)
- 3D model files:
gm1203bacpz-2-r7-etched.step/gm1203bacpz-2-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gm1203bacpz-2-r7.step/gm1203bacpz-2-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GONGMOSEMI datasheet (25 pp, sha256
f744d3090b584d94, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).