CY7C65211-24LTXIT from Cypress Semicon, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCB_0/GPIO_6	bidirectional	SCB/GPIO pin whose default function is RxD; function depends on the serial mode in Table 14 and GPIO options in Table 15.
2	SCB_5/GPIO_7	bidirectional	SCB/GPIO pin whose default function is DTR#; function depends on the serial mode in Table 14 and GPIO options in Table 15.
3	VSSD	power_in	Digital ground.
4	GPIO_8	bidirectional	General-purpose I/O, TRISTATE by default, configurable per Table 15.
5	GPIO_9	bidirectional	General-purpose I/O, TRISTATE by default, configurable per Table 15.
6	GPIO_10	bidirectional	General-purpose I/O, TRISTATE by default, configurable per Table 15.
7	GPIO_11	bidirectional	General-purpose I/O, POWER# by default, configurable per Table 15.
8	SUSPEND	output	Indicates the device is in suspend mode; can be configured active low or high using the configuration utility.
9	WAKEUP	input	Wakes the device from suspend mode; can be configured active low or high using the configuration utility, and must not be left unconnected.
10	USBDP	bidirectional	USB data signal plus; integrates a termination resistor and a 1.5-kΩ pull-up resistor.
11	USBDM	bidirectional	USB data signal minus; integrates a termination resistor.
12	VCCD	power_out	Should be decoupled to ground with a 1-µF capacitor or connected to a 1.8-V supply.
13	VSSD	power_in	Digital ground.
14	nXRES	input	Active-low chip reset; can be left unconnected or have a pull-up resistor if not used.
15	VBUS	power_in	VBUS supply, 3.15 V to 5.25 V.
16	VSSD	power_in	Digital ground.
17	VSSA	power_in	Analog ground.
18	GPIO_0	bidirectional	General-purpose I/O, TXLED# by default, configurable per Table 15; the only pin usable as CapSense Cmod.
19	GPIO_1	bidirectional	General-purpose I/O, RXLED# by default, configurable per Table 15.
20	SCB_1/GPIO_2	bidirectional	SCB/GPIO pin whose default function is DSR#; function depends on the serial mode in Table 14 and GPIO options in Table 15.
21	SCB_2/GPIO_3	bidirectional	SCB/GPIO pin whose default function is RTS#; function depends on the serial mode in Table 14 and GPIO options in Table 15.
22	SCB_3/GPIO_4	bidirectional	SCB/GPIO pin whose default function is CTS#; function depends on the serial mode in Table 14 and GPIO options in Table 15.
23	SCB_4/GPIO_5	bidirectional	SCB/GPIO pin whose default function is TxD; function depends on the serial mode in Table 14 and GPIO options in Table 15.
24	VDDD	power_in	Supply to the device core and interface, 1.71 to 5.5 V.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	QFN-24-EP(4x4)
Category	Communication Interface Chip/UART/485/232
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature		-55		100	°C		9
Ambient temperature with power supplied (Industrial)		-40		85	°C		9
Supply voltage VDDD	VDDD			6	V	Supply voltage to ground potential	9
Supply voltage VBUS	VBUS			6	V	Supply voltage to ground potential	9
Supply voltage VCCD	VCCD			1.95	V	Supply voltage to ground potential	9
GPIO voltage	VGPIO			0	V	VDDD + 0.5 V	9
ESD protection HBM				2.2	kV	HBM per JESD22-A114	9
Latch-up current				140	mA		9
Current per GPIO				25	mA		9
Ambient temperature under bias (Industrial)	TA	-40		85	°C		9
VBUS supply voltage	VBUS	3.15		5.25	V		9
VDDD supply voltage	VDDD	1.71		5.5	V		9
VCCD supply voltage	VCCD	1.71		1.89	V		9
VBUS supply voltage (3.3 V range)	VBUS	3.15	3.3	3.45	V	Set and configure the correct voltage range using a configuration utility for VBUS. Default 5 V.	9
VBUS supply voltage (5 V range)	VBUS	4.35	5	5.25	V	Set and configure the correct voltage range using a configuration utility for VBUS. Default 5 V.	9
VDDD supply voltage (1.8 V range)	VDDD	1.71	1.8	1.89	V	Used to set I/O and core voltage. Default 3.3 V.	9
VDDD supply voltage (3.3 V range)	VDDD	2	3.3	5.5	V	Used to set I/O and core voltage. Default 3.3 V.	9
External regulator voltage bypass	Cefc	1	1.3	1.6	µF	X5R ceramic or better	9
Output voltage (for core logic)	VCCD		1.8		V	Do not use this supply to drive the external device	9
Operating supply current	IDD1		20		mA	USB 2.0 FS, UART at 1-Mbps single channel, no GPIO switching.	9
USB Suspend supply current	IDD2		5		µA	Does not include current through a pull-up resistor on USBDP.	9
USB driver output impedance	Zout	28		44	Ω		9
Wakeup from USB Suspend mode	Twakeup		25		µs		9
Input voltage high threshold (CMOS)	VIH	0			V	CMOS Input; min 0.7 × VDDD	10
Input voltage low threshold (CMOS)	VIL			0	V	CMOS Input; max 0.3 × VDDD	10
LVTTL input high, VDDD > 2.7V	VIH	2			V	LVTTL input, VDDD > 2.7V	10
LVTTL input low, VDDD > 2.7V	VIL			0.8	V	LVTTL input, VDDD > 2.7V	10
CMOS output voltage high level (5 V)	VOH	0			V	IOH = 4 mA, VDDD = 5 V +/- 10%; min VDDD, 0.4	10
CMOS output voltage high level (3.3 V)	VOH	0			V	IOH = 4 mA, VDDD = 3.3 V +/- 10%; min VDDD, 0.6	10
CMOS output voltage high level (1.8 V)	VOH	0			V	IOH = 1 mA, VDDD = 1.8 V +/- 5%; min VDDD, 0.5	10
CMOS output voltage low level (5 V)	VOL			0.4	V	IOL = 8 mA, VDDD = 5 V +/- 10%	10
CMOS output voltage low level (3.3 V)	VOL			0.6	V	IOL = 8 mA, VDDD = 3.3 V +/- 10%	10
CMOS output voltage low level (1.8 V)	VOL			0.6	V	IOL = 4 mA, VDDD = 1.8 V +/- 5%	10
Pull-up resistor	Rpullup	3.5	5.6	8.5	kΩ		10
Pull-down resistor	Rpulldown	3.5	5.6	8.5	kΩ		10
Input leakage current (absolute value)	IIL			2	nA	25 °C, VDDD = 3.0 V	10
Input capacitance	CIN			7	pF		10
Input hysteresis LVTTL	Vhysttl	25	40		mV	LVTTL; VDDD > 2.7 V	10
Rise Time in Fast mode	TRiseFast1	2		12	ns	VDDD = 3.3 V/ 5.5 V, Cload = 25 pF	10
Fall Time in Fast mode	TFallFast1	2		12	ns	VDDD = 3.3 V/ 5.5 V, Cload = 25 pF	10
Rise Time in Slow mode	TRiseSlow1	10		60	ns	VDDD = 3.3 V/ 5.5 V, Cload = 25 pF	10
Fall Time in Slow mode	TFallSlow1	10		60	ns	VDDD = 3.3 V/ 5.5 V, Cload = 25 pF	10
Rise Time in Fast mode	TRiseFast2	2		20	ns	VDDD = 1.8 V, Cload = 25 pF	10
Fall Time in Fast mode	TFallFast2	20		100	ns	VDDD = 1.8 V, Cload = 25 pF	10
Rise Time in Slow mode	TRiseSlow2	2		20	ns	VDDD = 1.8 V, Cload = 25 pF	10
Fall Time in Slow mode	TFallSlow2	20		100	ns	VDDD = 1.8 V, Cload = 25 pF	10
Operating ambient temperature	TA	-40	25	85	°C		31
Package thermal resistance junction to ambient	THJ		18.4		°C/W		31

CAD (KiCad official)

Symbol: CY7C65211-24LTXIT
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: cy7c65211-24ltxit-etched.step / cy7c65211-24ltxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c65211-24ltxit.step / cy7c65211-24ltxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (38 pp, sha256 3f2aeacdf04634cf, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY7C65211-24LTXIT

Verified CY7C65211-24LTXIT

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README