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MCP6S93T-E

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Microchip Tech Programmable/Variable Gain Amplifiers (PGAs/VGAs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentoperational amplifier-comparatormcp6s93t-efactory-2.0.0extractor-text

Verified MCP6S93T-E

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MCP6S93T-E · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 40-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1wv51ngg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.35)
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mcp6s93t-e.kicad_sym✓ mcp6s93t-e.kicad_mod✓ mcp6s93t-e.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

MCP6S93T-E

Microchip Tech · Programmable/Variable Gain Amplifiers (PGAs/VGAs) · MSOP-10

MCP6S93T-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output Analog output, a low-impedance voltage source whose value is set by the selected gain, selected input (CH0, CH1) and the voltage at VREF.
2 CH0 input Analog input channel 0, a high-impedance CMOS input with low bias current that the internal MUX can select for amplification to the output.
3 CH1 input Analog input channel 1, a high-impedance CMOS input with low bias current that the internal MUX can select for amplification to the output.
4 VREF power_in External reference analog input that should be at a voltage between VSS and VDD and shifts the output voltage.
5 VSS power_in Negative power supply pin, connected to ground in a single-supply configuration.
6 CS input SPI chip select, a Schmitt-triggered CMOS logic input.
7 SI input SPI serial data input, a Schmitt-triggered CMOS logic input.
8 SO output SPI serial data output, a CMOS push-pull output that never goes High-Z and is forced low when CS goes high, supporting daisy-chaining.
9 SCK input SPI clock input, a Schmitt-triggered CMOS logic input.
10 VDD power_in Positive power supply pin, 2.5V to 5.5V above VSS, needing a local 0.01 µF to 0.1 µF bypass capacitor within 2 mm.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package MSOP-10
Category Operational Amplifier/Comparator
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS -4 4 mV G = +1 2
Power Supply Rejection Ratio PSRR 70 90 dB G = +1 (Note 1) 2
DC Gain Error G = +1 gE -0.2 0.2 % VOUT ≈ 0.3V to VDD − 0.3V 2
DC Gain Error G ≥ +2 gE -1 1 % VOUT ≈ 0.3V to VDD − 0.3V 2
Ladder Resistance RLAD 3.4 4.9 6.4 kΩ (Note 1) 3
Supply Voltage VDD 2.5 5.5 V 3
Minimum Valid Supply Voltage VDD_VAL 0.4 2 V Register data still valid 3
Quiescent Current IQ 0.4 1 1.6 mA IO = 0 (Note 3) 3
Input Leakage Current IIL -1 1 µA 5
Amplifier Output Leakage Current -1 1 µA In Shutdown mode 5
Input Rise/Fall Times (CS, SI, SCK) tRFI 2 µs (Note 1) 5
CS High Time tCSH 40 ns 5
SCK Edge to CS Fall Setup Time tCS0 10 ns SCK edge when CS is high 5
CS Fall to First SCK Edge Setup Time tCSSC 40 ns 5
SCK Frequency fSCK 10 MHz VDD = 5V (Note 2) 5
SCK High Time tHI 40 ns 5
SCK Low Time tLO 40 ns 5
SCK Last Edge to CS Rise Setup Time tSCCS 30 ns 5
CS Rise to SCK Edge Setup Time tCS1 100 ns SCK edge when CS is high 5
SI Setup Time tSU 40 ns 5
SI Hold Time tHD 10 ns 5
SCK to SO Valid Propagation Delay tDO 80 ns MCP6S93 5
CS Rise to SO Forced to Zero tSOZ 80 ns MCP6S93 5
Amplifier Output Turn-on Time tON 3.5 10 µs CS = 0.7 VDD to VOUT 90% point 5
Specified Temperature Range TA -40 125 °C (Note 1) 6
Operating Temperature Range TA -40 125 °C 6
Storage Temperature Range TA -65 150 °C 6
Supply Voltage VDD - VSS VDD-VSS 7 V 2
Current at Input Pin -2 2 mA 2
Current at Output and Supply Pins -30 30 mA 2
Junction Temperature TJ 150 °C 2
ESD protection HBM 4 kV all pins 2
ESD protection MM 200 V all pins 2
Thermal Resistance, 10L-MSOP θJA 143 °C/W 6
Input Offset Voltage Mismatch ΔVOS 0 µV Between inputs (CH0, CH1) 2
Input Offset Voltage Drift ΔVOS/ΔTA 1.8 µV/°C TA = -40°C to +125°C 2
Input Bias Current IB 1 pA CHx = VDD/2 2
Input Bias Current at 85°C IB 30 pA CHx = VDD/2, TA = +85°C 2
Input Bias Current at 125°C IB 600 pA CHx = VDD/2, TA = +125°C 2
DC Gain Drift G = +1 ΔG/ΔTA 0.0002 %/°C TA = -40°C to +125°C 2
DC Gain Drift G ≥ +2 ΔG/ΔTA 0.0004 %/°C TA = -40°C to +125°C 2
Ladder Resistance across Temperature ΔRLAD/ΔTA 0.028 %/°C TA = -40°C to +125°C (Note 1) 3
DC Output Non-linearity G = +1 VONL 0.18 % of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD = 5.0V 3
DC Output Non-linearity G ≥ +2 VONL 0.05 % of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD = 5.0V 3
Short Circuit Current ISC 25 mA 3
Quiescent Current, Shutdown Mode IQ_SHDN 30 pA IO = 0 (Note 3) 3
Slew Rate G = 1, 2 SR 4 V/µs G = 1, 2 4
Slew Rate G = 4, 5, 8, 10 SR 11 V/µs G = 4, 5, 8, 10 4
Slew Rate G = 16, 32 SR 22 V/µs G = 16, 32 4
Input Noise Voltage 0.1 Hz to 10 Hz Eni 4.5 µVP-P f = 0.1 Hz to 10 Hz (Note 2) 4
Input Noise Voltage Density eni 10 nV/√Hz f = 10 kHz (Note 2) 4
Input Noise Current Density ini 4 fA/√Hz f = 10 kHz 4
Channel Select Time tCH 1.5 µs CHx = 0.6V, CHy = 0.3V, G = 1, CHx to CHy select, CS = 0.7 VDD to VOUT 90% point 5
Gain Select Time tG 1 µs CHx = CHy = 0.3V, G = 5 to G = 1 select, CS = 0.7 VDD to VOUT 90% point 5
Amplifier Output Turn-off Time tOFF 1.5 µs CS = 0.7 VDD to VOUT 90% point 5
Output Rise/Fall Times (SO) tRFO 5 ns MCP6S93 5
Pin Capacitance CPIN 10 pF All digital I/O pins 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN), Narrow, 150 mil (SOIC) Foot Angle φ 048048 33

CAD (KiCad official)

  • Symbol: MCP6S93T-E
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: mcp6s93t-e-etched.step / mcp6s93t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp6s93t-e.step / mcp6s93t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (40 pp, sha256 4ff68087eb19cd44, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF