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ADM7150ARDZ-1.8
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Analog Devices Linear Voltage Regulators (LDO), SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADM7150ARDZ-1.8
Analog Devices · Linear Voltage Regulators (LDO) · SOIC-8-EP
ADM7150ARDZ-1.8 from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREG | power_in | Regulated input supply to the LDO amplifier; bypass VREG to GND with a 10 µF or greater capacitor and do not connect a load to ground. |
| 2 | VOUT | power_out | Regulated output voltage; bypass VOUT to GND with a 10 µF or greater capacitor. |
| 3 | BYP | passive | Low noise bypass capacitor; connect a 1 µF capacitor to GND to reduce noise and do not connect a load to ground. |
| 4 | GND | power_in | Ground connection. |
| 5 | REF_SENSE | input | REF_SENSE must be connected to the REF pin for proper operation and must not be connected to VOUT or GND. |
| 6 | REF | passive | Low noise reference voltage output; bypass REF to GND with a 1 µF capacitor, short REF_SENSE to REF for fixed output voltages, and do not connect a load to ground. |
| 7 | EN | input | Enable; drive EN high to turn the regulator on and low to turn it off, and connect EN to VIN for automatic startup. |
| 8 | VIN | power_in | Regulator input supply; bypass VIN to GND with a 10 µF or greater capacitor. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 4.5 | 16 | V | 3 | ||
| Operating supply current | IGND | 4.3 | 7 | mA | IOUT = 0 µA | 3 | |
| Operating supply current | IGND | 8.6 | 12 | mA | IOUT = 800 mA | 3 | |
| Shutdown current | IIN-SD | 0.1 | 3 | µA | VEN = 0 V | 3 | |
| Voltage accuracy | VOUT | -1 | 1 | % | IOUT = 10 mA, TJ = 25°C | 3 | |
| Voltage accuracy | VOUT | -2 | 2 | % | 1 mA < IOUT < 800 mA, over line, load and temperature | 3 | |
| Line regulation | ΔVOUT/ΔVIN | -0.01 | 0.01 | %/V | VIN = VOUT + 1.2 V or VOUT + 4.5 V, whichever is greater, to 16 V | 3 | |
| Load regulation | ΔVOUT/ΔIOUT | 0.4 | 1 | %/A | IOUT = 1 mA to 800 mA | 3 | |
| VOUT current-limit threshold | ILIMIT | 1 | 1.2 | 1.6 | A | 3 | |
| Dropout voltage | VDROPOUT | 0.3 | 0.5 | V | IOUT = 400 mA, VOUT = 5 V | 3 | |
| Dropout voltage | VDROPOUT | 0.6 | 1 | V | IOUT = 800 mA, VOUT = 5 V | 3 | |
| EN input logic high | ENHIGH | 3.2 | V | 4.5 V ≤ VIN ≤ 16 V | 4 | ||
| EN input logic low | ENLOW | 0.8 | V | 4.5 V ≤ VIN ≤ 16 V | 4 | ||
| EN input leakage current | IEN-LKG | 0.1 | 1 | µA | VEN = VIN or GND | 4 | |
| Minimum input capacitance | CIN | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum regulator capacitance | CREG | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum output capacitance | COUT | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum bypass capacitance | CBYP | 0.1 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum reference capacitance | CREF | 0.7 | µF | TA = −40°C to +125°C | 4 | ||
| Capacitor ESR | RESR | 0.001 | 0.2 | Ω | CREG, COUT, CIN, CREF; TA = −40°C to +125°C | 4 | |
| Capacitor ESR | RESR | 0.001 | 2 | Ω | CBYP; TA = −40°C to +125°C | 4 | |
| VIN to GND | -0.3 | 18 | V | 5 | |||
| VREG to GND | -0.3 | 6 | V | or VIN, whichever is less | 5 | ||
| VOUT to GND | -0.3 | 6 | V | or VREG, whichever is less | 5 | ||
| VOUT to BYP | -0.3 | 0.3 | V | ±0.3 V | 5 | ||
| EN to GND | -0.3 | 18 | V | 5 | |||
| BYP to GND | -0.3 | 6 | V | or VREG, whichever is less | 5 | ||
| REF to GND | -0.3 | 6 | V | or VREG, whichever is less | 5 | ||
| REF_SENSE to GND | -0.3 | 6 | V | 5 | |||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| Output noise | OUTNOISE | 1.6 | µV rms | 10 Hz to 100 kHz, independent of output voltage | 3 | ||
| Output noise | OUTNOISE | 1 | µV rms | 100 Hz to 100 kHz, independent of output voltage | 3 | ||
| Noise spectral density | NSD | 1.7 | nV/√Hz | 10 kHz to 1 MHz, independent of output voltage | 3 | ||
| VOUT pull-down resistance | VOUT-PULL | 600 | Ω | VEN = 0 V, VOUT = 1 V | 3 | ||
| VREG pull-down resistance | VREG-PULL | 34 | kΩ | VEN = 0 V, VREG = 1 V | 3 | ||
| VREF pull-down resistance | VREF-PULL | 800 | Ω | VEN = 0 V, VREF = 1 V | 3 | ||
| VBYP pull-down resistance | VBYP-PULL | 500 | Ω | VEN = 0 V, VBYP = 1 V | 3 | ||
| Thermal shutdown threshold | TSSD | 155 | °C | TJ rising | 3 | ||
| Thermal shutdown hysteresis | TSSD-HYS | 15 | °C | 3 | |||
| Input voltage rising UVLO | UVLORISE | 4.49 | V | 3 | |||
| Input voltage falling UVLO | UVLOFALL | 3.85 | V | 3 | |||
| UVLO hysteresis | UVLOHYS | 240 | mV | 3 | |||
| VREG rise UVLO | VREGUVLORISE | 3.1 | V | 3 | |||
| VREG fall UVLO | VREGUVLOFALL | 2.55 | V | 3 | |||
| VREG UVLO hysteresis | VREGUVLOHYS | 210 | mV | 3 | |||
| EN input logic hysteresis | ENHYS | 225 | mV | VIN = 5 V | 4 | ||
| Thermal resistance junction to ambient | θJA | 36.9 | °C/W | 8-Lead SOIC | 5 | ||
| Thermal resistance junction to case | θJC | 27.1 | °C/W | 8-Lead SOIC | 5 | ||
| Junction to board thermal characterization parameter | ΨJB | 18.6 | °C/W | 8-Lead SOIC | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | and the amount of copper used to solder the package GND pin | 19 |
CAD (KiCad official)
- Symbol:
ADM7150ARDZ-1.8 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
adm7150ardz-1-8-etched.step/adm7150ardz-1-8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adm7150ardz-1-8.step/adm7150ardz-1-8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
8c494e2a6e3928ea, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).