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SN74HCS174DR

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HCS174DR

Texas Instruments · Flip Flops · SOIC-16

SN74HCS174DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Clear input for all six channels, active low; a low level forces all Q outputs low regardless of D and CLK (Function Table, Table 8-1).
2 1Q output Channel 1 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
3 1D input Channel 1 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
4 2D input Channel 2 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
5 2Q output Channel 2 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
6 3D input Channel 3 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
7 3Q output Channel 3 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
8 GND power_in Ground reference for the device.
9 CLK input Clock input shared by all channels; data is transferred on the rising (positive-going) edge.
10 4Q output Channel 4 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
11 4D input Channel 4 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
12 5Q output Channel 5 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
13 5D input Channel 5 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
14 6D input Channel 6 D data input, sampled on the positive-going edge of CLK; Schmitt-trigger CMOS input.
15 6Q output Channel 6 push-pull CMOS output, Q, that follows the D input on the rising edge of CLK.
16 VCC power_in Positive supply; recommended operating range is 2 V to 6 V (nominal 5 V), with absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature TA -40 125 °C 4
Positive switching threshold VT+ 0.7 1.5 V VCC = 2 V 5
Positive switching threshold VT+ 1.7 3.15 V VCC = 4.5 V 5
Positive switching threshold VT+ 2.1 4.2 V VCC = 6 V 5
Negative switching threshold VT- 0.3 1 V VCC = 2 V 5
Negative switching threshold VT- 0.9 2.2 V VCC = 4.5 V 5
Negative switching threshold VT- 1.2 3 V VCC = 6 V 5
Hysteresis (VT+ - VT-) ΔVT 0.2 1 V VCC = 2 V 5
Hysteresis (VT+ - VT-) ΔVT 0.4 1.4 V VCC = 4.5 V 5
Hysteresis (VT+ - VT-) ΔVT 0.6 1.6 V VCC = 6 V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V 5
Input leakage current II -1000 1000 nA VI = VCC or 0; VCC = 6 V 5
Supply current ICC 0.1 2 µA VI = VCC or 0; IO = 0; VCC = 6 V 5
Clock frequency fclock 60 MHz CL = 50 pF; TA = 25°C; VCC = 2 V 5
Clock frequency fclock 180 MHz CL = 50 pF; TA = 25°C; VCC = 4.5 V 5
Clock frequency fclock 200 MHz CL = 50 pF; TA = 25°C; VCC = 6 V 5
Clock frequency fclock 40 MHz CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5
Clock frequency fclock 130 MHz CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 5
Clock frequency fclock 145 MHz CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 5
Pulse duration CLR low tw 8 ns CL = 50 pF; TA = 25°C; VCC = 2 V 5
Pulse duration CLR low tw 5 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 5
Pulse duration CLR low tw 12 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5
Pulse duration CLR low tw 6 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 5
Setup time, data tsu 12 ns CL = 50 pF; TA = 25°C; VCC = 2 V 5
Setup time, data tsu 5 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 5
Setup time, data tsu 18 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5
Setup time, data tsu 6 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 5
Propagation delay CLR to any output tpd 15 27 ns CL = 50 pF; TA = 25°C; VCC = 2 V 6
Propagation delay CLR to any output tpd 8 13 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 6
Propagation delay CLR to any output tpd 7 11 ns CL = 50 pF; TA = 25°C; VCC = 6 V 6
Propagation delay CLR to any output tpd 35 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 6
Propagation delay CLR to any output tpd 18 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 6
Propagation delay CLR to any output tpd 16 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 6
Transition time (any output) tt 9 ns CL = 50 pF; TA = 25°C; VCC = 2 V 6
Transition time (any output) tt 5 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 6
Transition time (any output) tt 4 ns CL = 50 pF; TA = 25°C; VCC = 6 V 6
Transition time (any output) tt 17 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 6
Transition time (any output) tt 8 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 6
Transition time (any output) tt 7 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 6
Junction-to-ambient thermal resistance RθJA 122.2 °C/W D (SOIC), 16 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 80.9 °C/W D (SOIC), 16 pins 4
Junction-to-board thermal resistance RθJB 80.6 °C/W D (SOIC), 16 pins 4

CAD (KiCad official)

  • Symbol: SN74HCS174DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs174dr-etched.step / sn74hcs174dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs174dr.step / sn74hcs174dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 ec37bbf3a4e2a4f7, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF