Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

PJMG40P60TE

PJSEMI · MOSFETs · TO-252

PJMG40P60TE from PJSEMI, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal of the P-channel MOSFET, with a maximum gate-source voltage of ±20 V and threshold of -1.2 to -2.5 V.
2 Drain passive Drain terminal, rated for -VDS of 60 V and continuous drain current of 40 A (pulsed 320 A) at 25°C case temperature.
3 Source passive Source terminal of the P-channel MOSFET, with body diode continuous forward current of 40 A.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package TO-252
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage -V(BR)DSS 60 V VGS=0V,ID=-250μA 2
Zero Gate Voltage Drain Current -IDSS 1 μA VDS=-60V,VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V,VDS=0V 2
Gate Threshold Voltage -VGS(th) 1.2 1.75 2.5 V VDS=VGS,ID=-250μA 2
Drain-Source On-Resistance RDS(on) 18 25 mΩ VGS=-10V,ID=-15A 2
Drain-Source On-Resistance RDS(on) 21 30 mΩ VGS=-4.5V,ID=-10A 2
Diode Forward Voltage -VSD 1.2 V VGS=0V,IS=-6A 2
Diode Forward Current -IS 40 A 2
Drain-Source Voltage -VDS 60 V 25℃ case temperature 1
Gate-Source Voltage VGS -20 20 V 25℃ case temperature 1
Drain Current-Continuous -ID 40 A 25℃ case temperature 1
Drain Current-Pulsed -IDM 320 A Note1 1
Maximum Power Dissipation PD 65 W 25℃ case temperature 1
Junction Temperature TJ 150 °C 1
Storage Temperature Range TSTG -55 150 °C 1
Single pulse avalanche energy EAS 90 mJ Note2 1
Thermal Resistance, Junction-to-Case RθJC 1.9 °C/W 1
Input Capacitance Ciss 1505 pF VDS=-25V,VGS=0V,f=1MHz 2
Output Capacitance Coss 302 pF VDS=-25V,VGS=0V,f=1MHz 2
Reverse Transfer Capacitance Crss 17 pF VDS=-25V,VGS=0V,f=1MHz 2
Total Gate Charge Qg 23 nC VDS=-30V,ID=-3A,VGS=0~-10V 2
Gate-Source Charge Qgs 4 nC VDS=-30V,ID=-3A,VGS=0~-10V 2
Gate-Drain Charge Qgd 3 nC VDS=-30V,ID=-3A,VGS=0~-10V 2
Turn-on Delay Time td(on) 7 nS VDD=-30V,ID=-4A,VGS=-10V,RGEN=6Ω 2
Turn-on Rise Time tr 5 nS VDD=-30V,ID=-4A,VGS=-10V,RGEN=6Ω 2
Turn-off Delay Time td(off) 65 nS VDD=-30V,ID=-4A,VGS=-10V,RGEN=6Ω 2
Turn-off Fall Time tf 20 nS VDD=-30V,ID=-4A,VGS=-10V,RGEN=6Ω 2
Forward Transconductance gFS 5 S VDS=-5V,ID=-1A 2
Gate Resistance Rg 7 Ω VDS=0V,VGS=0V,f=1MHz 2

CAD (KiCad official)

  • Symbol: PJMG40P60TE
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: pjmg40p60te-etched.step / pjmg40p60te-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pjmg40p60te.step / pjmg40p60te.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (5 pp, sha256 13d32c0aa9f22338, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF