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Contents

README

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SN74F10DR

Texas Instruments · Logic Gates · SOIC-14

SN74F10DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input NAND gate 1 input A; accepts -1.2 V to 7 V per absolute maximum ratings.
2 1B input NAND gate 1 input B; accepts -1.2 V to 7 V per absolute maximum ratings.
3 2A input NAND gate 2 input A; accepts -1.2 V to 7 V per absolute maximum ratings.
4 2B input NAND gate 2 input B; accepts -1.2 V to 7 V per absolute maximum ratings.
5 2C input NAND gate 2 input C; accepts -1.2 V to 7 V per absolute maximum ratings.
6 2Y output NAND gate 2 output (Y = 2A•2B•2C); IOH 1 mA, IOL 20 mA per recommended operating conditions.
7 GND power_in Ground; 0 V reference and power return.
8 3Y output NAND gate 3 output (Y = 3A•3B•3C); IOH 1 mA, IOL 20 mA per recommended operating conditions.
9 3A input NAND gate 3 input A; accepts -1.2 V to 7 V per absolute maximum ratings.
10 3B input NAND gate 3 input B; accepts -1.2 V to 7 V per absolute maximum ratings.
11 3C input NAND gate 3 input C; accepts -1.2 V to 7 V per absolute maximum ratings.
12 1Y output NAND gate 1 output (Y = 1A•1B•1C); IOH 1 mA, IOL 20 mA per recommended operating conditions.
13 1C input NAND gate 1 input C; accepts -1.2 V to 7 V per absolute maximum ratings.
14 VCC power_in Positive supply voltage; 4.5 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74F10DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f10dr-etched.step / sn74f10dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f10dr.step / sn74f10dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 906d204aa757f1d6, retrieved 2026-09-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF