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HG82C55AN

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HGSEMI I/O Expanders, DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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HG82C55AN

HGSEMI · I/O Expanders · DIP-40

HG82C55AN from HGSEMI, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional Port A bit 3, a universal 8-bit I/O line whose direction is set by writing a control word.
2 PA2 bidirectional Port A bit 2, a universal 8-bit I/O line whose direction is set by writing a control word.
3 PA1 bidirectional Port A bit 1, a universal 8-bit I/O line whose direction is set by writing a control word.
4 PA0 bidirectional Port A bit 0, a universal 8-bit I/O line whose direction is set by writing a control word.
5 RD input Active-low read input; when low, data is transferred from the HG82C55A to the CPU.
6 CS input Active-low chip select; low enables data transmission with the CPU, high puts the data bus in high impedance with no read or write while internal registers keep their state.
7 GND power_in Ground.
8 A1 input Port select (address) input that together with A0 selects port A, port B, port C or the control register, usually tied to the low-order address bits.
9 A0 input Port select (address) input that together with A1 selects port A, port B, port C or the control register, usually tied to the low-order address bits.
10 PC7 bidirectional Port C bit 7, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
11 PC6 bidirectional Port C bit 6, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
12 PC5 bidirectional Port C bit 5, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
13 PC4 bidirectional Port C bit 4, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
14 PC0 bidirectional Port C bit 0, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
15 PC1 bidirectional Port C bit 1, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
16 PC2 bidirectional Port C bit 2, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
17 PC3 bidirectional Port C bit 3, a universal I/O line that becomes a control pin when port A or B is used in mode 1 or 2, and supports bit set/reset when port C is an output.
18 PB0 bidirectional Port B bit 0, a universal 8-bit I/O line whose direction is set by writing a control word.
19 PB1 bidirectional Port B bit 1, a universal 8-bit I/O line whose direction is set by writing a control word.
20 PB2 bidirectional Port B bit 2, a universal 8-bit I/O line whose direction is set by writing a control word.
21 PB3 bidirectional Port B bit 3, a universal 8-bit I/O line whose direction is set by writing a control word.
22 PB4 bidirectional Port B bit 4, a universal 8-bit I/O line whose direction is set by writing a control word.
23 PB5 bidirectional Port B bit 5, a universal 8-bit I/O line whose direction is set by writing a control word.
24 PB6 bidirectional Port B bit 6, a universal 8-bit I/O line whose direction is set by writing a control word.
25 PB7 bidirectional Port B bit 7, a universal 8-bit I/O line whose direction is set by writing a control word.
26 VCC power_in +5V power supply (operating range 3 to 6 V, recommended 4.5 to 5.5 V).
27 D7 tri_state Data bus bit 7, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
28 D6 tri_state Data bus bit 6, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
29 D5 tri_state Data bus bit 5, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
30 D4 tri_state Data bus bit 4, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
31 D3 tri_state Data bus bit 3, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
32 D2 tri_state Data bus bit 2, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
33 D1 tri_state Data bus bit 1, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
34 D0 tri_state Data bus bit 0, a three-state bidirectional line carrying data, control words and bit set/reset data with the CPU.
35 RESET input Active-high reset input that clears the control register and internal registers, sets all ports to input mode (high impedance), clears port latches to 0 and sets all groups to mode 0.
36 WR input Active-low write input; when low, data or control words are transferred from the CPU to the HG82C55A.
37 PA7 bidirectional Port A bit 7, a universal 8-bit I/O line that can operate as a bidirectional port in mode 2.
38 PA6 bidirectional Port A bit 6, a universal 8-bit I/O line that can operate as a bidirectional port in mode 2.
39 PA5 bidirectional Port A bit 5, a universal 8-bit I/O line that can operate as a bidirectional port in mode 2.
40 PA4 bidirectional Port A bit 4, a universal 8-bit I/O line that can operate as a bidirectional port in mode 2.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-40
Category Interface ICs
Pins 40

CAD (KiCad official)

  • Symbol: HG82C55AN
  • Footprint: Package_DIP:DIP-40_W25.4mm
  • 3D model: DIP-40 (KiCad packages3D, STEP)
  • 3D model files: hg82c55an-etched.step / hg82c55an-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hg82c55an.step / hg82c55an.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (22 pp, sha256 eeed428e35f7d49d, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF