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AD5645RBRUZ-REEL7
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Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdownAD5645RBRUZ-REEL7
Analog Devices · Digital To Analog Converters (DACs) · TSSOP-14
AD5645RBRUZ-REEL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, or it can be tied permanently low. |
| 2 | ADDR1 | input | Three-state address input that sets the two least significant bits (A1, A0) of the 7-bit slave address. |
| 3 | VDD | power_in | Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. |
| 4 | VOUTA | output | Analog output voltage from DAC A, with rail-to-rail operation of the output amplifier. |
| 5 | VOUTC | output | Analog output voltage from DAC C, with rail-to-rail operation of the output amplifier. |
| 6 | POR | input | Power-on reset pin; tying it to GND powers up the device to 0 V and tying it to VDD powers up the device to midscale. |
| 7 | VREFIN/VREFOUT | bidirectional | Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input. |
| 8 | ADDR2 | input | Three-state address input that sets bits A3 and A2 of the 7-bit slave address. |
| 9 | CLR | input | Falling-edge sensitive asynchronous clear input that loads zero scale to all input and DAC registers and clears the output to 0 V. |
| 10 | VOUTD | output | Analog output voltage from DAC D, with rail-to-rail operation of the output amplifier. |
| 11 | VOUTB | output | Analog output voltage from DAC B, with rail-to-rail operation of the output amplifier. |
| 12 | GND | power_in | Ground reference point for all circuitry on the device. |
| 13 | SDA | bidirectional | Bidirectional open-drain serial data line that should be pulled to the supply with an external pull-up resistor. |
| 14 | SCL | input | Serial clock line used with SDA to clock data into or out of the 16-bit input register. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Operating Temperature Range, Industrial | -40 | 105 | °C | 10 | |||
| Storage Temperature Range | -65 | 150 | °C | 10 | |||
| Junction Temperature (TJ maximum) | TJ | 150 | °C | 10 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 10 | ||
| Relative Accuracy (INL), AD5645R | INL | 2 | 4 | LSB | 3 | ||
| Differential Nonlinearity (DNL), AD5645R | DNL | -0.5 | 0.5 | LSB | Guaranteed monotonic by design | 3 | |
| Offset Error | -10 | 1 | 10 | mV | 3 | ||
| Full-Scale Error | -0.5 | -0.1 | 0.5 | % FSR | All 1s loaded to DAC register | 3 | |
| Gain Error | -1 | 0.1 | 1 | % FSR | 3 | ||
| Zero-Code Error Drift | -2 | 2 | µV/°C | 3 | |||
| Gain Temperature Coefficient | -2.5 | 2.5 | ppm Of FSR/°C | 3 | |||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 3 | |||
| Capacitive Load Stability | 10 | nF | RL = 2 kΩ | 3 | |||
| Reference Current | 210 | 260 | µA | VREF = VDD = 5.5 V | 3 | ||
| Reference Output Voltage (2.5 V) | 2.495 | 2.505 | V | At ambient; VDD = 4.5 V to 5.5 V | 4 | ||
| Reference TC (2.5 V reference) | -5 | 5 | ppm/°C | 4 | |||
| Logic input current (ADDRx, CLR, LDAC, POR) | IIN | -1 | 1 | µA | 4 | ||
| Logic input current (SDA, SCL) | IIN | -1 | 1 | µA | 4 | ||
| Output Low Voltage (SDA) | VOL | 0.4 | V | ISINK = 3 mA | 4 | ||
| Output Low Voltage (SDA) | VOL | 0.6 | V | ISINK = 6 mA | 4 | ||
| Floating-State Leakage Current | -1 | 1 | µA | 4 | |||
| IDD (Normal Mode), internal reference off | IDD | 1 | 1.16 | mA | VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V | 4 | |
| IDD (Normal Mode), internal reference off | IDD | 0.9 | 1.05 | mA | VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V | 4 | |
| IDD (Normal Mode), internal reference on | IDD | 1.9 | 2.14 | mA | VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V | 4 | |
| IDD (Normal Mode), internal reference on | IDD | 1.4 | 1.59 | mA | VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V | 4 | |
| IDD (All Power-Down Modes), TSSOP | IDD | 0.48 | 1 | µA | VIH = VDD, VIL = GND (TSSOP); VDD = 3.6 V to 5.5 V | 4 | |
| Output Voltage Settling Time, AD5645R | tS | 3.5 | 5 | µs | ¼ to ¾ scale settling to ±0.5 LSB | 7 | |
| Zero-Code Error | 2 | 10 | mV | All 0s loaded to DAC register | 3 | ||
| DC Power Supply Rejection Ratio | PSRR | -100 | dB | DAC code = midscale; VDD = 5 V ± 10% | 3 | ||
| DC Crosstalk (Internal Reference) | 25 | µV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 3 | |||
| DC Crosstalk (Internal Reference) | 20 | µV/mA | Due to load current change | 3 | |||
| DC Crosstalk (Internal Reference) | 10 | µV | Due to powering down (per channel) | 3 | |||
| DC Crosstalk (External Reference) | 15 | µV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 3 | |||
| DC Crosstalk (External Reference) | 10 | µV/mA | Due to load current change | 3 | |||
| DC Crosstalk (External Reference) | 8 | µV | Due to powering down (per channel) | 3 | |||
| DC Output Impedance | 0.5 | Ω | 3 | ||||
| Short-Circuit Current | 30 | mA | VDD = 5 V | 3 | |||
| Power-Up Time | 4 | µs | Coming out of power-down mode; VDD = 5 V | 3 | |||
| Reference Input Impedance | 26 | kΩ | 3 | ||||
| Reference Output Impedance (2.5 V) | 7.5 | kΩ | 4 | ||||
| Pin Capacitance (ADDRx, CLR, LDAC, POR) | CIN | 2 | pF | 4 | |||
| Pin Capacitance (SDA, SCL) | CIN | 2 | pF | 4 | |||
| Floating-State Output Capacitance | 2 | pF | 4 | ||||
| Slew Rate | 1.8 | V/µs | 7 | ||||
| Digital-to-Analog Glitch Impulse | 5 | nV-s | 1 LSB change around major carry; TSSOP | 7 | |||
| Digital Feedthrough | 0.1 | nV-s | 7 | ||||
| Reference Feedthrough | -90 | dB | VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz | 7 | |||
| Digital Crosstalk | 0.1 | nV-s | 7 | ||||
| Analog Crosstalk (External Reference) | 1 | nV-s | External reference | 7 | |||
| Analog Crosstalk (Internal Reference) | 4 | nV-s | Internal reference | 7 | |||
| DAC-to-DAC Crosstalk (External Reference) | 1 | nV-s | External reference | 7 | |||
| DAC-to-DAC Crosstalk (Internal Reference) | 4 | nV-s | Internal reference | 7 | |||
| Multiplying Bandwidth | 340 | kHz | VREF = 2 V ± 0.1 V p-p | 7 | |||
| Total Harmonic Distortion | THD | -80 | dB | VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz | 7 | ||
| Output Noise Spectral Density | 120 | nV/√Hz | DAC code = midscale, 1 kHz | 7 | |||
| Output Noise Spectral Density | 100 | nV/√Hz | DAC code = midscale, 10 kHz | 7 | |||
| Output Noise | 15 | µV p-p | 0.1 Hz to 10 Hz | 7 | |||
| Thermal Impedance θJA, TSSOP | θJA | 150.4 | °C/W | TSSOP | 10 |
CAD (KiCad official)
- Symbol:
AD5645RBRUZ-REEL7 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
ad5645rbruz-reel7-etched.step/ad5645rbruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5645rbruz-reel7.step/ad5645rbruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (35 pp, sha256
92ae60d05500e362, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).