LT1793CN8#PBF from Analog Devices, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOS ADJ	passive	Offset voltage adjust pin; a 10k potentiometer with its wiper to V- gives a typical ±13mV adjustment range.
2	-IN	input	Inverting input of the JFET op amp, with typical bias current of 3pA and input capacitance of 1.5pF.
3	+IN	input	Non-inverting input of the JFET op amp, with typical bias current of 3pA and input resistance of 10^13 Ω in common mode.
4	V-	power_in	Negative supply, with supply voltage absolute maximum of ±20V and the offset-null potentiometer wiper tied here.
5	VOS ADJ	passive	Offset voltage adjust pin; connects to the other end of the offset-null potentiometer (10k to 200k range).
6	OUT	output	Op amp output, swinging ±13.0V min into 10k load at ±15V supplies with indefinite short-circuit duration.
7	V+	power_in	Positive supply, with supply voltage absolute maximum of ±20V and typical supply current of 4.2mA.
8	NC	unconnected	No internal connection.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	PDIP-8
Category	Amplifiers
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Offset Voltage	VOS		0.25	0.9	mV	TA=25°C, VS=±15V	2
Input Offset Voltage	VOS		0.45	1.6	mV	VS=±5V	2
Input Offset Current	IOS		2.5	15	pA	Warmed Up (Note 3)	2
Input Offset Current	IOS		0.7	4	pA	TJ=25°C (Note 6)	2
Input Bias Current	IB		4	20	pA	Warmed Up (Note 3)	2
Input Bias Current	IB		1.5	5	pA	TJ=25°C (Note 6)	2
Input Noise Voltage Density	en		6	8	nV/√Hz	fO=1000Hz	2
Input Voltage Range (positive)	VCM	13	13.5		V	Note 5	2
Input Voltage Range (negative)	VCM	-10.5	-11		V	Note 5	2
Common Mode Rejection Ratio	CMRR	81	96		dB	VCM=-10V to 13V	2
Power Supply Rejection Ratio	PSRR	83	95		dB	VS=±4.5V to ±20V	2
Large-Signal Voltage Gain	AVOL	900	4400		V/mV	VO=±12V, RL=10k	3
Large-Signal Voltage Gain	AVOL	400	3000		V/mV	VO=±10V, RL=1k	3
Output Voltage Swing	VOUT	13	13.2		V	RL=10k (printed ±)	3
Output Voltage Swing	VOUT	12	12.3		V	RL=1k (printed ±)	3
Slew Rate	SR	2.3	3.4		V/µs	RL ≥ 2k (Note 7)	3
Gain-Bandwidth Product	GBW	2.5	4.2		MHz	fO=100kHz	3
Supply Current	IS		4.2	5.2	mA	TA=25°C, VS=±15V	3
Supply Current	IS		4.2	5.15	mA	VS=±5V	3
Input Offset Voltage	VOS		1	3.5	mV	0°C ≤ TA ≤ 70°C	3
Input Offset Voltage	VOS		1.6	4.2	mV	VS=±5V, 0°C ≤ TA ≤ 70°C	3
Average Input Offset Voltage Drift	ΔVOS/ΔTemp		8	50	µV/°C	Note 6, 0°C ≤ TA ≤ 70°C	3
Input Offset Current	IOS		20	130	pA	0°C ≤ TA ≤ 70°C	3
Input Bias Current	IB		150	500	pA	0°C ≤ TA ≤ 70°C	3
Input Voltage Range (positive)	VCM	12.9	13.4		V	Note 5, 0°C ≤ TA ≤ 70°C	3
Input Voltage Range (negative)	VCM	-10	-10.8		V	Note 5, 0°C ≤ TA ≤ 70°C	3
Common Mode Rejection Ratio	CMRR	77	95		dB	VCM=-10V to 12.9V, 0°C ≤ TA ≤ 70°C	3
Power Supply Rejection Ratio	PSRR	81	94		dB	VS=±4.5V to ±20V, 0°C ≤ TA ≤ 70°C	3
Large-Signal Voltage Gain	AVOL	800	3400		V/mV	VO=±12V, RL=10k, 0°C ≤ TA ≤ 70°C	3
Large-Signal Voltage Gain	AVOL	400	2400		V/mV	VO=±10V, RL=1k, 0°C ≤ TA ≤ 70°C	3
Output Voltage Swing	VOUT	12.9	13.2		V	RL=10k (printed ±), 0°C ≤ TA ≤ 70°C	3
Output Voltage Swing	VOUT	11.9	12.15		V	RL=1k (printed ±), 0°C ≤ TA ≤ 70°C	3
Slew Rate	SR	2.2	3.3		V/µs	RL ≥ 2k (Note 7), 0°C ≤ TA ≤ 70°C	3
Gain-Bandwidth Product	GBW	2.2	3.3		MHz	fO=100kHz, 0°C ≤ TA ≤ 70°C	3
Supply Current	IS		4.2	5.3	mA	0°C ≤ TA ≤ 70°C	3
Supply Current	IS		4.2	5.25	mA	VS=±5V, 0°C ≤ TA ≤ 70°C	3
Supply Voltage		-20		20	V	printed ±20V	2
Differential Input Voltage		-40		40	V	printed ±40V	2
Input Voltage		-20		20	V	Equal to Supply Voltage, printed ±20V	2
Operating Temperature Range		-40		85	°C		2
Storage Temperature Range		-65		150	°C		2
Lead Temperature				300	°C	Soldering, 10 sec	2
Maximum Junction Temperature	TJMAX			150	°C	N8 package	2
Thermal Resistance Junction to Ambient	θJA		80		°C/W	N8 package	2
Input Noise Voltage	en		2.4		µVP-P	0.1Hz to 10Hz	2
Input Noise Voltage Density	en		11.5		nV/√Hz	fO=10Hz	2
Input Noise Current Density	in		1		fA/√Hz	fO=10Hz, fO=1kHz (Note 4)	2
Input Capacitance	CIN		1.5		pF		2
Input Capacitance	CIN		2		pF	VS=±5V	2
Offset Voltage Adjustment Range			13		mV	RPOT (to VEE) = 10k	3

CAD (KiCad official)

Symbol: LT1793CN8#PBF
Footprint: Package_DIP:DIP-8_W7.62mm
3D model: PDIP-8 (KiCad packages3D, STEP)
3D model files: lt1793cn8-pbf-etched.step / lt1793cn8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1793cn8-pbf.step / lt1793cn8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (12 pp, sha256 ecd71b31649ed80e, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LT1793CN8#PBF

Verified LT1793CN8#PBF

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README