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Contents

README

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TPS3836H30DBVR

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TPS3836H30DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CT passive Capacitor time delay pin; connect to GND for 10 ms reset delay or to VDD for 200 ms reset delay.
2 GND power_in Ground.
3 MR input Manual reset input; activates RESET output when pulled low; connect to VDD to minimize current consumption when unused.
4 RESET output Active-low output reset; asserts low when VDD falls below VIT (2.79 V typical) or MR is pulled low; returns high after reset delay time when VDD rises above VIT + VHYS and MR is inactive.
5 VDD power_in Input supply voltage for 3.0 V supervision; monitored against threshold of 2.79 V nominal.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TPS3836H30DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps3836h30dbvr-etched.step / tps3836h30dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3836h30dbvr.step / tps3836h30dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 6a2b25929a6d0dfb, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF