A 3 A step-down (buck) DC-DC converter with the high-side switch integrated, in SOIC-8, a step up from a controller like the MC34063 because it needs no external FET. It accepts a wide 3.5 to 28 V input and regulates down to as low as 0.8 V, switching at a fixed 570 kHz so the external inductor and capacitors stay small. An enable pin, adjustable soft-start (SS), and a voltage-mode control loop with external compensation (COMP) give a clean, protected supply with current limit and thermal shutdown. It is a common choice for turning a 12 V or 24 V rail into 5 V or 3.3 V at a couple of amps. The BOOT pin bootstraps the high-side gate; PH is the switch node.

Pinout

Pin	Name	Type	Function
1	BOOT	power_out	Bootstrap capacitor node for the internal high-side N-channel MOSFET gate driver. A 0.1-µF ceramic capacitor is required between BOOT and PH. Absolute-max BOOT-to-GND is 38 V and BOOT-PH is 8 V; if the BOOT-PH voltage falls below the minimum, the high-side MOSFET is turned off until the bootstrap cap is refreshed.
2	VIN	power_in	3.5-V to 28-V input supply pin. Absolute max 30 V; recommended operating range 3.5-28 V. Bypass to GND with a low-ESR ceramic capacitor placed close to the pin.
3	EN	input	Enable input. Float to enable; pull below 1.25 V (typ enable threshold) to disable. A resistor divider from VIN to EN to GND programs the input UVLO with two resistors (uses the small hysteresis current, ~-1 µA at threshold and ~-4 µA at threshold+50 mV). Absolute-max 6 V.
4	SS	input	Slow-start pin. An external capacitor from SS to GND sets the output voltage rise time (charge current ~2 µA at V(SS)=0.4 V). SS-to-VSENSE matching typ 10 mV. Absolute-max 3 V.
5	VSENSE	input	Inverting input of the internal transconductance (gm) error amplifier. Connect the feedback resistor divider from the regulated output to VSENSE (reference voltage 0.8 V typ, 0.772-0.828 V). Absolute-max 3 V.
6	COMP	output	Error-amplifier output and input to the PWM comparator. Connect the type-II frequency compensation network (typically Rc + Cc series to GND with optional high-frequency Cp) to this pin. Error-amp gm 92 µmhos, ±7 µA source/sink typ. Absolute-max 3 V.
7	GND	power_in	Device ground. Return for all internal circuitry; must be tied to system ground (and to the exposed PowerPAD on the DDA package).
8	PH	power_out	Switch node - source of the internal high-side power MOSFET. Connect the external inductor to PH and the freewheeling Schottky rectifier cathode to PH. Absolute-max range -0.6 V to 30 V (10-ns transients to -5 V allowed); peak sink current up to 9 A.

Key specifications

Parameter	Value
Type	Step-down (buck) converter, integrated FET
Output current	3 A
Input voltage	3.5-28 V
Output voltage	down to 0.8 V
Switching frequency	570 kHz
Control	voltage-mode, external COMP
Protection	current limit + thermal shutdown
Package	SOIC-8

Ordering variants

Same part, different packaging or reel option.

TPS54331DR (SOIC-8)
TPS54331D (SOIC-8, tube)

CAD (KiCad official)

Symbol: TPS54331 (generated from datasheet; KiCad has no symbol)
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 cf72dfd0ac69eec6, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF