M24C32-DRDW8TP from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	E0	input	Chip Enable input that sets the least significant bit of the 3-bit chip enable address in the device select code, to be tied to VCC or VSS and read as low when left floating.
2	E1	input	Chip Enable input that sets the middle bit of the 3-bit chip enable address in the device select code, to be tied to VCC or VSS and read as low when left floating.
3	E2	input	Chip Enable input that sets the most significant bit of the 3-bit chip enable address in the device select code, to be tied to VCC or VSS and read as low when left floating.
4	VSS	power_in	Ground, the reference for the VCC supply voltage.
5	SDA	bidirectional	Serial Data input/output with an open-drain output that needs a pull-up resistor to VCC.
6	SCL	input	Serial Clock input used to strobe data on SDA in and to output data on SDA out.
7	WC	input	Active-high Write Control input that disables write operations to the entire memory array when driven high, and enables writes when driven low or left floating.
8	VCC	power_in	Supply voltage pin, operating range 1.7 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	TSSOP-8
Category	Memory
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Ambient operating temperature (absolute maximum rating)		-40	130	°C		26
Storage temperature	TSTG	-65	150	°C		26
Input or output range	VIO	-0.5	6.5	V		26
DC output current	IOL		5	mA	SDA = 0	26
Supply voltage (absolute maximum)	VCC	-0.5	6.5	V		26
Electrostatic pulse (Human Body model)	VESD		4000	V	Human Body model, AEC-Q100-002	26
Supply voltage (voltage range R)	VCC	1.7	5.5	V		27
Ambient operating temperature	TA	-40	105	°C		27
Write cycle endurance	Ncycle		4e+06		TA ≤ 25 °C, 1.7 V < VCC < 5.5 V	27
Write cycle			1.2e+06		TA = 85 °C, 1.7 V < VCC < 5.5 V	27
Write cycle			900000		TA = 105 °C, 1.7 V < VCC < 5.5 V	27
Input capacitance (SDA)	CIN		8	pF		28
Input capacitance (other pins)	CIN		6	pF		28
Input impedance (E2, E1, E0, WC)	ZL	30		kΩ	VIN < 0.3 VCC	28
Input impedance (E2, E1, E0, WC)	ZH	500		kΩ	VIN > 0.7 VCC	28
Input leakage current (SCL, SDA)	ILI	-2	2	µA	VIN = VSS or VCC, device in Standby mode	29
Output leakage current	ILO	-2	2	µA	SDA in Hi-Z, external voltage applied on SDA: VSS or VCC	29
Supply current (Read)	ICC		2	mA	fC = 400 kHz, VCC = 5.5 V	29
Supply current (Read)	ICC		1	mA	fC = 400 kHz, VCC = 1.7 V	29
Supply current (Write)	ICC0		2	mA	During tW	29
Standby supply current	ICC1		2.5	µA	Device not selected, t° = 105 °C, VIN = VSS or VCC, VCC = 1.7 V	29
Standby supply current	ICC1		5	µA	Device not selected, t° = 105 °C, VIN = VSS or VCC, VCC = 5.5 V	29
Input low voltage (SCL, SDA, WC)	VIL	-0.45		V		29
Input high voltage (SCL, SDA)	VIH		6.5	V		29
Output low voltage	VOL		0.4	V	IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V	29
Output low voltage	VOL		0.3	V	IOL = 1 mA, VCC = 1.7 V	29
Internal reset threshold voltage	VRES	0.5	1.5	V		29
Clock frequency (400 kHz)	fC		400	kHz		30
Clock pulse width high (400 kHz)	tCHCL	600		ns		30
Clock pulse width low (400 kHz)	tCLCH	1300		ns		30
SDA (out) fall time (400 kHz)	tQL1QL2	20	120	ns	CL = 10 pF	30
Data in set up time (400 kHz)	tDXCH	100		ns		30
Data in hold time (400 kHz)	tCLDX	0		ns		30
Data out hold time (400 kHz)	tCLQX	100		ns		30
Clock low to next data valid (access time) tAA (400 kHz)	tCLQV		900	ns		30
Start condition setup time (400 kHz)	tCHDL	600		ns		30
Start condition hold time (400 kHz)	tDLCL	600		ns		30
Stop condition set up time (400 kHz)	tCHDH	600		ns		30
Time between Stop condition and next Start condition (400 kHz)	tDHDL	1300		ns		30
Write time (400 kHz)	tW		4	ms		30
Pulse width ignored, input filter on SCL and SDA (400 kHz)	tNS		80	ns	single glitch	30
Clock frequency (1 MHz)	fC	0	1	MHz		31
Clock pulse width high (1 MHz)	tCHCL	260		ns		31
Clock pulse width low (1 MHz)	tCLCH	400		ns		31
SDA (out) fall time (1 MHz)	tQL1QL2		120	ns		31
Data in setup time (1 MHz)	tDXCH	50		ns		31
Data in hold time (1 MHz)	tCLDX	0		ns		31
Data out hold time (1 MHz)	tCLQX	100		ns		31
Clock low to next data valid (access time) tAA (1 MHz)	tCLQV		450	ns		31
Start condition setup time (1 MHz)	tCHDL	250		ns		31
Start condition hold time (1 MHz)	tDLCL	250		ns		31
Stop condition setup time (1 MHz)	tCHDH	250		ns		31
Time between Stop condition and next Start condition (1 MHz)	tDHDL	500		ns		31
Write time (1 MHz)	tW		4	ms		31
Pulse width ignored, input filter on SCL and SDA (1 MHz)	tNS		80	ns		31

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	TLEAD Lead temperature during soldering see note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST	26

CAD (KiCad official)

Symbol: M24C32-DRDW8TP
Footprint: Package_SO:TSSOP-8_4.4x3mm_P0.65mm
3D model: TSSOP-8 (KiCad packages3D, STEP)
3D model files: m24c32-drdw8tp-etched.step / m24c32-drdw8tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m24c32-drdw8tp.step / m24c32-drdw8tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (42 pp, sha256 f6bab274b6f60a18, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

M24C32-DRDW8TP

Verified M24C32-DRDW8TP

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README