STM32L471VET6TR from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TRACECK, TIM3_ETR, TSC_G7_IO1, FMC_A23, SAI1_MCLK_A and EVENTOUT.
2	PE3	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TRACED0, TIM3_CH1, TSC_G7_IO2, FMC_A19, SAI1_SD_B and EVENTOUT.
3	PE4	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A and EVENTOUT.
4	PE5	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, FMC_A21, SAI1_SCK_A and EVENTOUT.
5	PE6	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TRACED3, TIM3_CH4, FMC_A22, SAI1_SD_A and EVENTOUT; additional function RTC_TAMP3/WKUP3.
6	VBAT	power_in	Backup-domain supply, 1.55 V to 3.6 V, powering the RTC and backup registers in VBAT mode.
7	PC13	bidirectional	I/O supplied through the power switch, limited to 3 mA sink, 2 MHz at 30 pF maximum and not usable as a current source; additional functions RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2.
8	PC14-OSC32_IN	bidirectional	I/O supplied through the power switch with the same 3 mA and 2 MHz / 30 pF limits as PC13; also the LSE oscillator input OSC32_IN.
9	PC15-OSC32_OUT	bidirectional	I/O supplied through the power switch with the same 3 mA and 2 MHz / 30 pF limits as PC13; also the LSE oscillator output OSC32_OUT.
10	VSS	power_in	Ground pin for the digital supply domain.
11	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.
12	PH0-OSC_IN	bidirectional	5 V-tolerant (FT) I/O with alternate function EVENTOUT; also the HSE oscillator input OSC_IN.
13	PH1-OSC_OUT	bidirectional	5 V-tolerant (FT) I/O with alternate function EVENTOUT; also the HSE oscillator output OSC_OUT.
14	NRST	bidirectional	Bidirectional reset pin with embedded weak pull-up resistor.
15	PC0	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions LPTIM1_IN1, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX and LPTIM2_IN1; additional function ADC123_IN1.
16	PC1	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions LPTIM1_OUT, I2C3_SDA, DFSDM1_CKIN4 and LPUART1_TX; additional function ADC123_IN2.
17	PC2	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions LPTIM1_IN2, SPI2_MISO and DFSDM1_CKOUT; additional function ADC123_IN3.
18	PC3	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A and LPTIM2_ETR; additional function ADC123_IN4.
19	VSSA	power_in	Analog ground reference for the ADC, DAC, OPAMP, COMP and VREF.
20	VREF-	power_in	Negative ADC reference voltage, which must equal VSSA.
21	VREF+	power_in	Positive ADC reference voltage: 2 V up to VDDA when VDDA is at least 2 V, and VDDA when VDDA is below 2 V.
22	VDDA	power_in	Analog supply, 1.62 V to 3.6 V when ADC or COMP is used, 1.8 V minimum when DAC or OPAMP is used.
23	PA0	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and SAI1_EXTCLK; additional function OPAMP1_VINP, ADC12_IN5 and RTC_TAMP2/WKUP1.
24	PA1	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA (Fm+ capable), alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX and TIM15_CH1N; additional function OPAMP1_VINM and ADC12_IN6.
25	PA2	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions TIM2_CH3, TIM5_CH3, USART2_TX, SAI2_EXTCLK and TIM15_CH1; additional functions ADC12_IN7 and WKUP4/LSCO.
26	PA3	bidirectional	3.6 V-tolerant (TT) I/O with analog switch function supplied by VDDA, alternate functions TIM2_CH4, TIM5_CH4, USART2_RX and TIM15_CH2; additional functions OPAMP1_VOUT and ADC12_IN8.
27	VSS	power_in	Ground pin for the digital supply domain.
28	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.
29	PA4	bidirectional	3.6 V-tolerant (TT) I/O with analog switch function supplied by VDDA, alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B and LPTIM2_OUT; additional functions ADC12_IN9 and DAC1_OUT1.
30	PA5	bidirectional	3.6 V-tolerant (TT) I/O with analog switch function supplied by VDDA, alternate functions TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK and LPTIM2_ETR; additional functions ADC12_IN10 and DAC1_OUT2.
31	PA6	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3 and TIM16_CH1; additional functions OPAMP2_VINP and ADC12_IN11.
32	PA7	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA (Fm+ capable), alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2 and TIM17_CH1; additional functions OPAMP2_VINM and ADC12_IN12.
33	PC4	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate function USART3_TX; additional functions COMP1_INM and ADC12_IN13.
34	PC5	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate function USART3_RX; additional functions COMP1_INP, ADC12_IN14 and WKUP5.
35	PB0	bidirectional	3.6 V-tolerant (TT) I/O with analog switch function supplied by VDDA, alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1 and COMP1_OUT; additional functions OPAMP2_VOUT and ADC12_IN15.
36	PB1	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0 and LPTIM2_IN1; additional functions COMP1_INM and ADC12_IN16.
37	PB2	bidirectional	5 V-tolerant I/O with analog switch function supplied by VDDA, alternate functions RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0 and EVENTOUT; additional function COMP1_INP.
38	PE7	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B and EVENTOUT.
39	PE8	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B and EVENTOUT.
40	PE9	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B and EVENTOUT.
41	PE10	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B and EVENTOUT.
42	PE11	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_NCS, FMC_D8 and EVENTOUT.
43	PE12	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9 and EVENTOUT.
44	PE13	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10 and EVENTOUT.
45	PE14	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11 and EVENTOUT.
46	PE15	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_BKIN, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12 and EVENTOUT.
47	PB10	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, COMP1_OUT and SAI1_SCK_A.
48	PB11	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS and COMP2_OUT.
49	VSS	power_in	Ground pin for the digital supply domain.
50	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.
51	PB12	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI2_FS_A and TIM15_BKIN.
52	PB13	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI2_SCK_A and TIM15_CH1N.
53	PB14	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI2_MCLK_A and TIM15_CH1.
54	PB15	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SWPMI1_SUSPEND, SAI2_SD_A and TIM15_CH2.
55	PD8	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions USART3_TX, FMC_D13 and EVENTOUT.
56	PD9	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions USART3_RX, FMC_D14, SAI2_MCLK_A and EVENTOUT.
57	PD10	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions USART3_CK, TSC_G6_IO1, FMC_D15, SAI2_SCK_A and EVENTOUT.
58	PD11	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions USART3_CTS, TSC_G6_IO2, FMC_A16, SAI2_SD_A, LPTIM2_ETR and EVENTOUT.
59	PD12	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM4_CH1, USART3_RTS_DE, TSC_G6_IO3, FMC_A17, SAI2_FS_A, LPTIM2_IN1 and EVENTOUT.
60	PD13	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM4_CH2, TSC_G6_IO4, FMC_A18, LPTIM2_OUT and EVENTOUT.
61	PD14	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM4_CH3, FMC_D0 and EVENTOUT.
62	PD15	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM4_CH4, FMC_D1 and EVENTOUT.
63	PC6	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, SDMMC1_D6, SAI2_MCLK_A and EVENTOUT.
64	PC7	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, SDMMC1_D7, SAI2_MCLK_B and EVENTOUT.
65	PC8	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM3_CH3, TIM8_CH3, TSC_G4_IO3, SDMMC1_D0 and EVENTOUT.
66	PC9	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1 and EVENTOUT.
67	PA8	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT and EVENTOUT.
68	PA9	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH2, USART1_TX, TIM15_BKIN and EVENTOUT.
69	PA10	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH3, USART1_RX, TIM17_BKIN and EVENTOUT.
70	PA11	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1 and EVENTOUT.
71	PA12	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM1_ETR, USART1_RTS_DE, CAN1_TX and EVENTOUT.
72	PA13 (JTMS-SWDIO)	bidirectional	5 V-tolerant (FT) I/O that after reset is the JTMS-SWDIO debug function with internal pull-up enabled; also alternate function IR_OUT and EVENTOUT.
73	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.
74	VSS	power_in	Ground pin for the digital supply domain.
75	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.
76	PA14 (JTCK-SWCLK)	bidirectional	5 V-tolerant (FT) I/O that after reset is the JTCK-SWCLK debug function with internal pull-down enabled; also alternate function EVENTOUT.
77	PA15 (JTDI)	bidirectional	5 V-tolerant (FT) I/O that after reset is the JTDI debug function with internal pull-up enabled; also alternate functions TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, SAI2_FS_B and EVENTOUT.
78	PC10	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, SDMMC1_D2, SAI2_SCK_B and EVENTOUT.
79	PC11	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B and EVENTOUT.
80	PC12	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, SDMMC1_CK, SAI2_SD_B and EVENTOUT.
81	PD0	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2 and EVENTOUT.
82	PD1	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3 and EVENTOUT.
83	PD2	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, SDMMC1_CMD and EVENTOUT.
84	PD3	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, FMC_CLK and EVENTOUT.
85	PD4	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, FMC_NOE and EVENTOUT.
86	PD5	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions USART2_TX, FMC_NWE and EVENTOUT.
87	PD6	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions DFSDM1_DATIN1, USART2_RX, FMC_NWAIT, SAI1_SD_A and EVENTOUT.
88	PD7	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions DFSDM1_CKIN1, USART2_CK, FMC_NE1 and EVENTOUT.
89	PB3 (JTDO-TRACESWO)	bidirectional	3.6 V-tolerant (TT_a) I/O with analog switch function supplied by VDDA; after reset it is the JTDO-TRACESWO debug function, with alternate functions TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B and EVENTOUT.
90	PB4 (NJTRST)	bidirectional	3.6 V-tolerant (TT_a) I/O with analog switch function supplied by VDDA; after reset it is the NJTRST debug function with internal pull-up enabled, with alternate functions TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, SAI1_MCLK_B and TIM17_BKIN.
91	PB5	bidirectional	5 V-tolerant (FT_a) I/O with analog switch function supplied by VDDA, alternate functions LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B and TIM16_BKIN.
92	PB6	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable, with analog switch function supplied by VDDA, alternate functions LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, TSC_G2_IO3, SAI1_FS_B and TIM16_CH1N; additional function COMP2_INP.
93	PB7	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable, with analog switch function supplied by VDDA, alternate functions LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, FMC_NL and TIM17_CH1N; additional functions COMP2_INM and PVD_IN.
94	BOOT0	input	Dedicated BOOT0 input pin, which accepts up to 9 V per Table 20.
95	PB8	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A and TIM16_CH1.
96	PB9	bidirectional	5 V-tolerant (FT_f) I/O, Fm+ capable, with alternate functions IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, SDMMC1_D5, SAI1_FS_A and TIM17_CH1.
97	PE0	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions TIM4_ETR, FMC_NBL0, TIM16_CH1 and EVENTOUT.
98	PE1	bidirectional	5 V-tolerant (FT) bidirectional I/O with alternate functions FMC_NBL1, TIM17_CH1 and EVENTOUT.
99	VSS	power_in	Ground pin for the digital supply domain.
100	VDD	power_in	Standard operating supply, 1.71 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage (VDD, VDDA, VDDIO2, VBAT)	VDDX - VSS	-0.3		4	V	including VDD, VDDA, VDDIO2, VBAT	97
Input voltage on any other pins	VIN			4	V	min printed as VSS-0.3	97
Input voltage on BOOT0 pin	VIN			9	V	BOOT0 pin, min printed as VSS	97
Total current into sum of all VDD power lines (source)	∑IVDD			150	mA		98
Total current out of sum of all VSS ground lines (sink)	∑IVSS			150	mA		98
Maximum current into each VDD power pin (source)	IVDD(PIN)			100	mA		98
Maximum current out of each VSS ground pin (sink)	IVSS(PIN)			100	mA		98
Output current sunk by any I/O and control pin except FT_f	IIO(PIN)			20	mA		98
Output current sourced by any I/O and control pin	IIO(PIN)			20	mA		98
Total output current sunk by sum of all I/Os and control pins	∑IIO(PIN)			100	mA		98
Total output current sourced by sum of all I/Os and control pins	∑IIO(PIN)			100	mA		98
Storage temperature range	TSTG	-65		150	°C		98
Maximum junction temperature	TJ			150	°C		98
Internal AHB clock frequency	fHCLK	0		80	MHz		99
Standard operating voltage	VDD	1.71		3.6	V		99
PG[15:2] I/Os supply voltage	VDDIO2	1.08		3.6	V	At least one I/O in PG[15:2] used	99
Analog supply voltage	VDDA	1.62		3.6	V	ADC or COMP used	99
Backup operating voltage	VBAT	1.55		3.6	V		99
Power dissipation at TA = 85 °C, LQFP100	PD			476	mW	TA = 85 °C for suffix 6	99
Ambient temperature for suffix 6, maximum power dissipation	TA	-40		85	°C	suffix 6 version, maximum power dissipation	100
Junction temperature range, suffix 6	TJ	-40		105	°C	Suffix 6 version	100
Brown-out reset threshold 0, rising edge	VBOR0	1.62	1.66	1.7	V	Rising edge	101
Brown-out reset threshold 0, falling edge	VBOR0	1.6	1.64	1.69	V	Falling edge	101
Reset temporization after BOR0 is detected	tRSTTEMPO		250	400	μs	VDD rising	101
Internal reference voltage	VREFINT	1.182	1.212	1.232	V	-40 °C < TA < +130 °C	103
Internal reference voltage spread over the temperature range	∆VREFINT		5	7.5	mV	VDD = 3 V	103
Average temperature coefficient	TCoeff		30	50	ppm/°C	-40°C < TA < +130°C	103
Long term stability	ACoeff		300	1000	ppm	1000 hours, T = 25°C	103
Average voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	103
Supply current in Run mode, Range 1, 80 MHz	IDD_ALL(Run)		10.5	12.1	mA	Range 1, fHCLK 80 MHz, all peripherals disable, 85 °C, code from Flash ART enable	106
Supply current in Low-power run mode, fMSI 2 MHz	IDD_ALL(LPRun)		413	579	µA	fHCLK = fMSI = 2 MHz, all peripherals disable, 85 °C	106
Supply current in Stop 2 mode, RTC disabled, 3 V	IDD_ALL(Stop 2)		15.4	39	µA	VDD 3 V, RTC disabled, 85 °C	112
Supply current in Standby mode, RTC disabled, 3.6 V	IDD_ALL(Standby)		2608	6520	nA	VDD 3.6 V, backup registers retained, no independent watchdog, 85 °C	116
Supply current in Shutdown mode, RTC disabled, 3.6 V	IDD_ALL(Shutdown)		2041	5103	nA	VDD 3.6 V, backup registers retained, RTC disabled, 85 °C	117
Backup domain supply current, RTC disabled, 3 V	IDD_VBAT		264	660	nA	VBAT 3 V, RTC disabled, 85 °C	119

CAD (KiCad official)

Symbol: STM32L471VET6TR
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: stm32l471vet6tr-etched.step / stm32l471vet6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l471vet6tr.step / stm32l471vet6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (229 pp, sha256 2a91fd04e0793619, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM32L471VET6TR

Verified STM32L471VET6TR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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