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MCP73832T-5ACI
Public Made by Adomby adom
Microchip Tech Battery Management ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP73832T-5ACI
Microchip Tech · Battery Management ICs · SOT-23-5
MCP73832T-5ACI from Microchip Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STAT | output | Charge status output for an LED or a host microcontroller with pull-up resistor; open-drain output on the MCP73832. |
| 2 | VSS | power_in | Battery management 0V reference, connected to the negative terminal of the battery and input supply. |
| 3 | VBAT | power_out | Battery charge control output connected to the positive battery terminal (drain of internal P-channel pass MOSFET), bypassed to VSS with a minimum of 4.7 µF. |
| 4 | VDD | power_in | Battery management input supply, recommended [VREG (typical) + 0.3V] to 6V, bypassed to VSS with a minimum of 4.7 µF. |
| 5 | PROG | input | Current regulation set pin: a resistor to VSS scales preconditioning, fast charge and termination currents, and floating the pin disables the charge controller. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-5 |
| Category | Power Supply Chip |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3.75 | 6 | V | 3 | ||
| Regulated Output Voltage | VREG | 4.466 | 4.5 | 4.534 | V | MCP7383X-5; VDD = [VREG(typical)+1V], IOUT = 10 mA, TA = -5°C to +55°C | 3 |
| Supply Current (Charging) | ISS | 510 | 1500 | µA | Charging | 3 | |
| Supply Current (Charge Complete, No Battery) | ISS | 53 | 200 | µA | Charge Complete, No Battery | 3 | |
| Supply Current (PROG Floating) | ISS | 25 | 50 | µA | PROG Floating | 3 | |
| Supply Current (VDD < VBAT - 50 mV) | ISS | 1 | 5 | µA | VDD < (VBAT - 50 mV) | 3 | |
| Supply Current (VDD < VSTOP) | ISS | 0.1 | 2 | µA | VDD < VSTOP | 3 | |
| UVLO Start Threshold | VSTART | 3.3 | 3.45 | 3.6 | V | VDD Low-to-High | 3 |
| UVLO Stop Threshold | VSTOP | 3.2 | 3.38 | 3.5 | V | VDD High-to-Low | 3 |
| Line Regulation | /(ΔVBAT/VBAT)/ΔVDD/ | 0.09 | 0.3 | %/V | VDD = [VREG(typical)+1V] to 6V, IOUT = 10 mA | 3 | |
| Load Regulation | /ΔVBAT/VBAT/ | 0.05 | 0.3 | % | IOUT = 10 mA to 50 mA, VDD = [VREG(typical)+1V] | 3 | |
| Fast Charge Current Regulation | IREG | 90 | 100 | 110 | mA | PROG = 10 kΩ | 3 |
| Fast Charge Current Regulation | IREG | 450 | 505 | 550 | mA | PROG = 2.0 kΩ, Note 1 | 3 |
| Fast Charge Current Regulation | IREG | 12.5 | 14.5 | 16.5 | mA | PROG = 67 kΩ, TA = -5°C to +55°C | 3 |
| Precondition Current Ratio | IPREG / IREG | 7.5 | 10 | 12.5 | % | PROG = 2.0 kΩ to 10 kΩ | 4 |
| Precondition Voltage Threshold Ratio | VPTH / VREG | 64 | 66.5 | 69 | % | VBAT Low-to-High | 4 |
| Charge Termination Current Ratio | ITERM / IREG | 5.6 | 7.5 | 9.4 | % | PROG = 2.0 kΩ to 10 kΩ | 4 |
| Recharge Voltage Threshold Ratio | VRTH / VREG | 94 | 96.5 | 99 | % | VBAT High-to-Low | 4 |
| Battery Detection Current | IBAT_DET | 0.6 | 6 | µA | VBAT Source Current | 4 | |
| No-Battery-Present Impedance | ZNO_BAT | 7 | MΩ | VBAT Impedance ≥ ZNO_BAT for No Battery condition, Note 1 | 4 | ||
| Output Reverse Leakage Current | IDISCHARGE | 0.15 | 2 | µA | PROG Floating | 4 | |
| Output Reverse Leakage Current | IDISCHARGE | 0.25 | 2 | µA | VDD Floating | 4 | |
| Output Reverse Leakage Current | IDISCHARGE | -5.5 | -15 | µA | Charge Complete | 4 | |
| Status Sink Current | ISINK | 25 | mA | 4 | |||
| Status Low Output Voltage | VOL | 0.4 | 1 | V | ISINK = 4 mA | 4 | |
| Status Input Leakage Current | ILK | 0.03 | 1 | µA | High-Impedance | 4 | |
| Charge Impedance Range | RPROG | 2 | 67 | kΩ | 4 | ||
| Minimum Shutdown Impedance | RPROG | 70 | 200 | kΩ | 4 | ||
| UVLO Start Delay | tSTART | 5 | ms | VDD Low-to-High | 5 | ||
| Transition Time Out of Preconditioning | tDELAY | 1 | ms | VBAT < VPTH to VBAT > VPTH | 5 | ||
| Current Rise Time Out of Preconditioning | tRISE | 1 | ms | IOUT Rising to 90% of IREG | 5 | ||
| Termination Comparator Filter | tTERM | 0.4 | 1.3 | 3.2 | ms | Average IOUT Falling | 5 |
| Charge Comparator Filter | tCHARGE | 0.4 | 1.3 | 3.2 | ms | Average VBAT | 5 |
| Status Output Turn-Off | tOFF | 200 | µs | ISINK = 1 mA to 0 mA | 5 | ||
| Status Output Turn-On | tON | 200 | µs | ISINK = 0 mA to 1 mA | 5 | ||
| Specified Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Supply Voltage | VDD | 7 | V | 3 | |||
| All Inputs and Outputs w.r.t. VSS | -0.3 | V | -0.3 to (VDD+0.3)V | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| ESD Human Body Model | 4 | kV | 1.5 kΩ in Series with 100 pF | 3 | |||
| Pass Transistor ON-Resistance | RDSON | 350 | mΩ | VDD = 3.75V, TJ = 105°C | 4 | ||
| Thermal Shutdown Die Temperature | TSD | 150 | °C | 5 | |||
| Die Temperature Hysteresis | TSDHYS | 10 | °C | 5 | |||
| Thermal Resistance, 5-Lead SOT-23 | θJA | 230 | °C/W | 4-Layer JC51-7 Standard Board, Natural Convection | 5 |
CAD (KiCad official)
- Symbol:
MCP73832T-5ACI - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
mcp73832t-5aci-etched.step/mcp73832t-5aci-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp73832t-5aci.step/mcp73832t-5aci.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (29 pp, sha256
75297f2a52355993, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).