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LM53601MQDSXRQ1
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Texas Instruments DC-DC Converters, WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM53601MQDSXRQ1
Texas Instruments · DC-DC Converters · WSON-10-EP(3x3)
LM53601MQDSXRQ1 from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Regulator switch node that connects to the output inductor; absolute maximum SW to GND is -0.3 V to VIN+0.3 V. |
| 2 | BOOT | input | High-side gate driver upper supply rail; connect a 100-nF capacitor from SW to BOOT, and BOOT to SW is limited to 3.6 V absolute maximum. |
| 3 | VCC | power_out | Internal 3-V regulator output that supplies the internal control circuits; connect a high-quality 1.0-µF capacitor from this pin to GND on adjustable versions, and VCC is limited to 3.6 V absolute maximum. |
| 4 | FB | input | On the adjustable version, this is the output voltage feedback input, connected to the output through a voltage divider that sets the output; FB to GND is limited to 5.5 V absolute maximum and the adjustment range is 3.3 V to 6 V. |
| 5 | BIAS | power_in | On the adjustable version, this is the power source for the VCC regulator; connect it to the output node with a 10-nF bypass capacitor placed immediately adjacent to the pin, and BIAS to GND is limited to 16 V absolute maximum. |
| 6 | RESET | output | Open-drain reset output that needs a current-limiting pull-up to a suitable supply, reads high when the regulator is OK and low on a fault or when EN is low; RESET to GND is limited to 8 V with 8 mA maximum sink current. |
| 7 | EN | input | Enable input where high turns the regulator on and low turns it off; it may be tied to VIN but must not float, and EN to GND is limited to 42 V (≤100 ms, ≤1% duty). |
| 8 | VIN | power_in | Input supply to the regulator with an operating range of 3.8 V to 36 V after startup and a 42 V absolute maximum; connect input bypass capacitors directly between this pin and GND. |
| 9 | SYNC/MODE | input | Multifunction mode input tolerant up to VIN: a valid external clock forces PWM and synchronizes the switching on its rising edge, high forces PWM at the internal clock, low selects AUTO mode with diode emulation at light load, and it must not float. |
| 10 | GND | power_in | Power ground that should be bypassed to VIN immediately adjacent to this pin. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | -0.3 | 42 | V | 5 | |||
| SW to GND | -0.3 | V | 5 | ||||
| BOOT to SW | -0.3 | 3.6 | V | 5 | |||
| EN to GND | -0.3 | 42 | V | 5 | |||
| BIAS to GND (ADJ version) | -0.3 | 16 | V | 5 | |||
| FB to GND (ADJ version) | -0.3 | 5.5 | V | 5 | |||
| RESET to GND | -0.3 | 8 | V | 5 | |||
| RESET sink current | 8 | mA | 5 | ||||
| SYNC/MODE to GND | -0.3 | 42 | V | 5 | |||
| VCC | -0.3 | 3.6 | V | 5 | |||
| Storage temperature | Tstg | -40 | 150 | °C | 5 | ||
| Input voltage range after startup | 3.8 | 36 | V | 5 | |||
| Output adjustment range (LM53601-Q1-ADJ) | 3.3 | 6 | V | 5 | |||
| Load current range LM53601-Q1 | 0 | 1000 | mA | 5 | |||
| Operating junction temperature | -40 | 150 | °C | 5 | |||
| Initial output voltage accuracy | VFB | -1 | 1 | % | Vin = 3.8 V to 36 V, Tj = 25°C, Open Loop | 6 | |
| Initial output voltage accuracy | VFB | -1.5 | 1.5 | % | Vin = 3.8 V to 36 V, Open Loop | 6 | |
| Bias current into BIAS pin (ADJ) | IB | 46 | 80 | µA | Vin = 13.5 V, Not switching, Vbias = 5 V, Mode = 0 V | 6 | |
| Minimum input voltage to operate (rising) | Vin_UVLO | 3.2 | 3.6 | 3.75 | V | Rising | 6 |
| Minimum input voltage hysteresis | Vin_UVLO_hyst | 0.2 | 0.3 | 0.35 | V | Hysteresis | 6 |
| RESET upper threshold voltage | Vreset_OV | 105 | 106.5 | 110 | % | Rising, % of Vout | 6 |
| RESET lower threshold voltage | Vreset_UV | 92 | 94 | 97 | % | Falling, % Vout | 6 |
| Switching frequency, spread spectrum center | Fsw | 1.89 | 2.1 | 2.4 | MHz | VIN = 13.5 V, center frequency with spread spectrum, PWM operation | 7 |
| Switching frequency, without spread spectrum | Fsw | 1.89 | 2.1 | 2.4 | MHz | VIN = 13.5 V, without spread spectrum, PWM operation | 7 |
| Sync frequency range | FSYNC | 1.9 | 2.1 | 2.3 | MHz | Output setting + 1 V < VIN < 18 V | 7 |
| Sync input duty cycle range | DSYNC | 25 | 75 | % | High state input < 5.5 V and > 2.3 V | 7 | |
| SYNC/MODE input hysteresis | VSYNC/MODE | 0.185 | 1 | V | 7 | ||
| Frequency span of spread spectrum operation | FSSS | -4 | 4 | % | 7 | ||
| High side switch current limit (LM53601-Q1) | IL_HS | 1.5 | 1.83 | 2.1 | A | Duty cycle approaches 0% | 7 |
| Low side switch current limit (LM53601-Q1) | IL_LS | 1 | 1.2 | 1.43 | A | LM53601-Q1 | 7 |
| Enable input threshold voltage - rising | VEN | 1.7 | 2 | V | Enable rising | 7 | |
| Enable threshold hysteresis | VEN_HYST | 0.4 | 0.55 | V | 7 | ||
| Reference voltage for ADJ option | Vref | 0.993 | 1 | 1.007 | V | Tj = 25°C | 8 |
| Reference voltage for ADJ option | Vref | 0.985 | 1 | 1.015 | V | 8 | |
| Rdson of RESET output | RRESET | 50 | 120 | Ω | 8 | ||
| Thermal shutdown rising threshold | TSD | 151 | 167 | 185 | °C | 8 | |
| Thermal shutdown falling threshold | TSDF | 140 | 157 | °C | 8 | ||
| Output voltage ADJ option (FPWM) | Vout_ADJ | -2 | 2 | % | VIN = VOUT + 0.6 V to 36 V, IOUT = 100 mA, FPWM mode | 8 | |
| Output voltage ADJ option (Auto mode) | Vout_ADJ | -2 | 2.5 | % | VIN = VOUT + 0.6 V to 36 V, IOUT = 100 µA to 100 mA, Auto mode | 8 | |
| Minimum switch on time | ton | 50 | 80.5 | ns | VIN = 18 V, IOUT = 500 mA | 9 | |
| Minimum switch off time | toff | 90 | 125 | ns | IOUT = 500 mA | 9 | |
| Delay time to RESET high signal | treset_act | 4 | 6 | 8 | ms | 9 | |
| Soft-start time | tSS | 1.3 | 3 | 4.5 | ms | Time from first SW node pulse to Vref at 90%, VIN ≥ 4.2 V | 9 |
| Operating quiescent current | IQ | 6.5 | µA | Vin = 13.5 V, Not switching, Vbias = 5 V | 6 | ||
| Input current to VIN node (VOUT = 3.3 V) | IQ_VIN | 23 | µA | VIN = 13.5 V, VOUT = 3.3 V, IOUT = 0 A | 8 | ||
| Shutdown quiescent current | ISD | 1.8 | µA | EN = 0, VIN = 13.5 V, Tj = 25°C | 6 | ||
| Negative current limit (LM53601-Q1) | IL_NEG | -0.7 | A | MODE/SYNC = High | 7 | ||
| High side MOSFET Rdson | Rdson | 220 | mΩ | High side MOSFET | 7 | ||
| Low side MOSFET Rdson | Rdson | 200 | mΩ | Low side MOSFET | 7 | ||
| Internal Vcc voltage | Vcc | 3.05 | V | VIN = 13.5 V, Vbias = 0 V | 7 | ||
| Internal Vcc input under voltage lock-out | Vcc_UVLO | 2.7 | V | VCC rising | 7 | ||
| Minimum input voltage for proper RESET function | Vreset_valid | 1.5 | V | 50 µA pull-up to RESET pin, EN = 0 V, Tj = 25°C | 6 | ||
| Minimum input to output voltage differential without inductor DCR drop | VDROP1 | 0.6 | V | VOUT = 3.3 V, IOUT = 1000 mA, +2/–3% output accuracy | 8 | ||
| Maximum switch duty cycle | Dmax | 76 | % | Fsw = 2.1 MHz | 8 | ||
| Input current from FB to AGND | IFB | 20 | nA | FB = 1 V | 8 | ||
| Thermal shutdown hysteresis | TSD_hyst | 10 | °C | 8 | |||
| Junction-to-ambient thermal resistance (DSX WSON) | RθJA | 46.2 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (DSX WSON) | RθJC | 31.5 | °C/W | 6 | |||
| Junction-to-board thermal resistance (DSX WSON) | RθJB | 20.9 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance (DSX WSON) | RθJC(bot) | 4.1 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
LM53601MQDSXRQ1 - Footprint:
Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lm53601mqdsxrq1-etched.step/lm53601mqdsxrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm53601mqdsxrq1.step/lm53601mqdsxrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
d174c97c59a34282, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).