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GM1203BACPZ-1-R7
Public Made by Adomby adom
GONGMOSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownGM1203BACPZ-1-R7
GONGMOSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(3.5x3.5)
GM1203BACPZ-1-R7 from GONGMOSEMI, in a QFN-20(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND, placed as close to the pin as possible, is required for stability. |
| 2 | SNS | passive | Output sense pin, connected to the output through an internal R0 resistor; connect it to the load side of the output only when the VOUT programming pins are used, otherwise leave it floating. |
| 3 | FB | input | Feedback pin to the error amplifier; a 10 nF feed-forward capacitor between FB and OUT, placed close to the device, is recommended. |
| 4 | PG | output | Open-drain, active-high power-good output that indicates the output has reached the PG rising threshold, requiring an external pull-up of 10 kΩ to 100 kΩ and rated for a PG current of −5 mA maximum. |
| 5 | 50mV | input | VOUT programming pin that adds 50 mV to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 6 | 100mV | input | VOUT programming pin that adds 100 mV to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 7 | 200mV | input | VOUT programming pin that adds 200 mV to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 8 | GND | power_in | Ground pin that must be connected with low impedance to the other GND pin(s) and the exposed pad. |
| 9 | 400mV | input | VOUT programming pin that adds 400 mV to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 10 | 800mV | input | VOUT programming pin that adds 800 mV to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 11 | 1.6V | input | VOUT programming pin that adds 1.6 V to the output when connected to GND, and is set to SNS or left floating otherwise. |
| 12 | BIAS | power_in | Bias supply pin that lowers dropout and improves DC and AC performance at VIN ≤ 2.2 V and requires a 10 µF or larger capacitor to GND; it must be left floating or grounded if unused, and at least 3 V must be applied to it when VIN is below 1.5 V. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin where an external capacitor to GND reduces reference noise and sets soft-start, with 10 nF or more recommended and a charge current of 4.0 µA to 11.5 µA. |
| 14 | EN | input | Enable pin where a logic high above 1.1 V enables the device and a logic low below 0.4 V disables it, with a maximum rating of 6.5 V, and it must be tied to IN or BIAS if enable control is not used. |
| 15 | IN | power_in | Input supply pin with a 1.1 V to 6.5 V operating range that requires a 10 µF or larger ceramic capacitor to GND placed as close to the pin as possible. |
| 16 | IN | power_in | Input supply pin with a 1.1 V to 6.5 V operating range that requires a 10 µF or larger ceramic capacitor to GND placed as close to the pin as possible. |
| 17 | IN | power_in | Input supply pin with a 1.1 V to 6.5 V operating range that requires a 10 µF or larger ceramic capacitor to GND placed as close to the pin as possible. |
| 18 | GND | power_in | Ground pin that must be connected with low impedance to the other GND pin(s) and the exposed pad. |
| 19 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND, placed as close to the pin as possible, is required for stability. |
| 20 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND, placed as close to the pin as possible, is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GONGMOSEMI |
| Package | QFN-20(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (line, load, over temperature) | -1 | 1 | % | 0.5 V ≤ VOUT ≤ 3.65 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 9 | ||
| Accuracy with BIAS | -1 | 1.3 | % | VIN = 1.1 V, VOUT = 0.5V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 9 | ||
| GM1203B output voltage range, pin-programmed | VFB | 0.8 | 3.95 | V | 使用引脚编程 (pin programming) | 9 | |
| GM1203B output voltage range, external resistor divider | VFB | 0.8 | 5.5 | V | 使用外部电阻 (external resistors), excludes resistor tolerance | 9 | |
| Minimum IN voltage for UVLO (with BIAS) | VUVLO | 0.98 | 1.085 | V | VBIAS = 3.0 V, TJ = −40°C to +125°C | 9 | |
| Minimum IN voltage for UVLO (without BIAS) | VUVLO1 | 1.32 | 1.49 | V | TJ = −40°C to +125°C, VIN rising | 9 | |
| Minimum BIAS input voltage for UVLO | VBIAS_UVLO | 2.2 | 2.9 | V | VIN = 1.1 V, VBIAS rising | 9 | |
| Dropout voltage, 3 A | VDO | 140 | 260 | mV | VIN = 1.5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3 A | VDO | 115 | 220 | mV | VIN = 5.4 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3 A with BIAS | VDO | 120 | 210 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Output current limit | ILIM | 3.7 | 4.2 | 6.7 | A | VOUT forced to 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 9 |
| EN pin low-level input voltage | VEN_IL | 0 | 0.4 | V | 9 | ||
| EN pin high-level input voltage | VEN_IH | 1.1 | 6.5 | V | 9 | ||
| EN pin current | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 9 | |
| PG falling threshold | VPG_FALLING | 82 | 91 | 93 | % × VOUT | 9 | |
| PG pin low-level output voltage | VPG_OL | 0.4 | V | VOUT < VPG_FALLING, IPG = -1 mA | 9 | ||
| PG pin leakage current | IPG_LK | 1 | µA | VOUT > VPG_FALLING + VPG_HYS, VPG = 6.5 V | 9 | ||
| NR/SS charging current | INR/SS | 4 | 9 | 11.5 | µA | VNR/SS = GND, VIN = 6.5 V | 9 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 9 | |
| Absolute max: IN, BIAS, PG, EN to GND voltage | -0.3 | 7 | V | 8 | |||
| Absolute max: NR/SS, FB to GND voltage | -0.3 | 3.6 | V | 8 | |||
| Absolute max: SNS, OUT to GND voltage | -0.3 | V | Upper limit printed as VIN+0.3 V | 8 | |||
| Absolute max: 50mV…1.6V output-setting pins to GND voltage | -0.3 | V | Upper limit printed as VOUT+0.3 V | 8 | |||
| Absolute max: PG current | -5 | mA | 8 | ||||
| Absolute max: storage temperature | -65 | 150 | °C | 8 | |||
| Operating temperature range | TJ | -40 | 125 | °C | Non-M grade (GM1203BACPZ); the −55°C to +125°C range applies to M variants | 8 | |
| Thermal resistance, junction to ambient, 20-pin 3.5 mm × 3.5 mm QFN | θJA | 43.4 | °C/W | Worst case, device soldered to PCB (JEDEC high-K 4-layer board) | 8 | ||
| Input voltage, no BIAS | VIN | 1.5 | 6.5 | V | Without BIAS supply | 18 | |
| Input voltage, with BIAS | VIN | 1.1 | 6.5 | V | When VIN < 1.5 V, BIAS must be at least 3 V | 18 | |
| BIAS supply voltage | VBIAS | 3 | 6.5 | V | Required when VIN < 1.5 V | 9 | |
| Input capacitor (IN to GND) | CIN | 10 | µF | Ceramic, placed close to IN pins | 6 | ||
| Output capacitor (OUT to GND) | COUT | 47 | µF | Ceramic, 22 µF or more effective capacitance | 18 | ||
| BIAS to GND capacitor | CBIAS | 10 | µF | When BIAS is used | 6 | ||
| NR/SS to GND capacitor | CNR/SS | 10 | nF | Recommended, placed close to pin | 6 | ||
| Feed-forward capacitor (FB to OUT) | CFF | 10 | nF | Recommended, FB to OUT | 18 | ||
| PG pull-up resistor | RPG | 10 | 100 | kΩ | Open-drain PG to external supply | 19 | |
| Quiescent (GND pin) current, shutdown | IGND | 18 | µA | Shutdown, VIN = 6.5 V, VEN = 0.5 V | 9 | ||
| GND pin current | IGND | 15 | mA | VIN = 6.5 V, IOUT = 5 mA | 9 | ||
| BIAS pin current | IBIAS | 16 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT = 0.8 V, IOUT = 3 A | 9 | ||
| Line regulation | ΔVOUT/ΔVIN | 0.1 | mV/V | VIN = Max(VOUT + 0.4V, 1.5 V) to 6.5 V | 9 | ||
| Load regulation | ΔVOUT/ΔIOUT | 0.2 | mV/A | 5 mA ≤ IOUT ≤ 3 A | 9 | ||
| UVLO hysteresis (with BIAS) | VUVLO_HYS | 100 | mV | VBIAS = 3.0 V | 9 | ||
| UVLO hysteresis (without BIAS) | VUVLO1_HYS | 115 | mV | 9 | |||
| BIAS UVLO hysteresis | VBIAS_UVLO_HYS | 200 | mV | VIN = 1.1 V | 9 | ||
| PG hysteresis, rising | VPG_HYS | 2 | % × VOUT | 9 | |||
| Internal reference voltage (NR/SS pin) | VNR/SS | 0.5 | V | 10 | |||
| PSRR | PSRR | 68 | dB | f = 10 kHz, VOUT = 0.8 V, VBIAS = 5.0 V; VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| PSRR | PSRR | 51 | dB | f = 1 MHz, VOUT = 0.8 V, VBIAS = 5.0 V; VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| PSRR | PSRR | 58 | dB | f = 10 kHz, VOUT = 5.0 V; VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| PSRR | PSRR | 43 | dB | f = 1 MHz, VOUT = 5.0 V; VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| Output noise voltage | VN | 3 | µVRMS | BW = 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.5 V or 0.8 V, VBIAS = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| Output noise voltage | VN | 14.8 | µVRMS | BW = 10 Hz to 100 kHz, VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 10 | ||
| Thermal shutdown temperature | TSD | 150 | °C | Shutdown threshold, temperature rising | 10 | ||
| Thermal shutdown hysteresis | TSD_HYS | 20 | °C | Restart threshold, temperature falling | 10 |
CAD (KiCad official)
- Symbol:
GM1203BACPZ-1-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: QFN-20(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gm1203bacpz-1-r7-etched.step/gm1203bacpz-1-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gm1203bacpz-1-r7.step/gm1203bacpz-1-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GONGMOSEMI datasheet (25 pp, sha256
f744d3090b584d94, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).