A 12-stage binary ripple counter in high-speed CMOS, SOIC-16. Each clock pulse increments a 12-bit count, and the twelve outputs (QA through QL) present the running total, so any output is the clock divided by a power of two (QA is divide-by-2, QL is divide-by-4096). A single asynchronous clear resets everything to zero. It is the compact way to generate a set of related clock divisions, build long timers, or produce a slow tick from a fast oscillator. Runs 2-6 V. Pin-identical to the CD4040.

Pinout

Pin	Name	Type	Function
1	QL	output	Counter stage 12 output (Q12, MSB). Push-pull CMOS output, ±4 mA drive at 5 V. Toggles on the falling edge of stage 11's output; frequency = fCLK / 4096.
2	QF	output	Counter stage 6 output (Q6). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 64.
3	QE	output	Counter stage 5 output (Q5). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 32.
4	QG	output	Counter stage 7 output (Q7). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 128.
5	QD	output	Counter stage 4 output (Q4). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 16.
6	QC	output	Counter stage 3 output (Q3). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 8.
7	QB	output	Counter stage 2 output (Q2). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 4.
8	GND	power_in	Ground / negative supply return. 0 V reference for VCC and all logic levels.
9	QA	output	Counter stage 1 output (Q1, LSB). Push-pull CMOS output, ±4 mA drive at 5 V. Toggles on each falling edge of CLK; frequency = fCLK / 2.
10	CLK	input	Clock input. Counter advances on the high-to-low (falling-edge) transition. Standard CMOS logic input: VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Max clock frequency = 25 MHz at VCC = 6 V.
11	CLR	input	Asynchronous master reset (active high). A high level asynchronously clears the counter and forces all Q outputs low, independent of CLK. Standard CMOS logic input.
12	QI	output	Counter stage 9 output (Q9). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 512.
13	QH	output	Counter stage 8 output (Q8). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 256.
14	QJ	output	Counter stage 10 output (Q10). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 1024.
15	QK	output	Counter stage 11 output (Q11). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 2048.
16	VCC	power_in	Positive supply input. Operating range 2 V to 6 V (absolute max 7 V). Bypass with a 0.1 µF ceramic close to the pin; a paralleled 1 µF is also recommended. ICC ≤ 80 µA (74HC) with static inputs.

Key specifications

Parameter	Value
Type	12-stage binary ripple counter
Outputs	12 (QA-QL, powers of two)
Division	divide-by-2 up to divide-by-4096
Clock	negative-edge triggered
Reset	asynchronous clear (active-high)
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

SN74HC4040D (SOIC-16, tube)
SN74HC4040DR (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 4xxx:4040 (pin-compatible with 74HC4040)
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 ad1231c1bceb2364, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF