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DGD05463M10-13
Public Made by Adomby adom
Diodes Incorporated Gate Drive ICs, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDGD05463M10-13
Diodes Incorporated · Gate Drive ICs · MSOP-10
DGD05463M10-13 from Diodes Incorporated, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side and logic supply; recommended 4.5V to 14V (absolute max -0.3 to +14V), with an external bootstrap Schottky diode needed for VCC of 4.5V to 4.9V. |
| 2 | VB | power_in | High-side floating supply; operates from VS+4.2V to VS+14V, absolute max -0.3 to +60V. |
| 3 | HO | output | High-side gate drive output with 1.5A source / 2.5A sink capability, swinging between VS and VB. |
| 4 | VS | power_in | High-side floating supply return (offset), logic operation for VS of -5V to +50V. |
| 5 | NC | unconnected | No connection; no internal connection. |
| 6 | DT | passive | Deadtime control pin, deadtime set by resistor RDT (e.g. 70ns typ at 10kΩ, 430ns typ at 100kΩ). |
| 7 | EN | input | Logic input enable, a logic low turns off the gate driver; VENIH min 1.5V, VENIL max 0.7V. |
| 8 | IN | input | Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO; VIH min 2.4V, VIL max 0.8V. |
| 9 | COM | power_in | Low-side and logic return (ground). |
| 10 | LO | output | Low-side gate drive output with 1.5A source / 2.5A sink capability, swinging between COM and VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | MSOP-10 |
| Category | Power Management |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 Input Voltage | VIH | 2.4 | V | VCC = VBS = 12V | 5 | ||
| Logic 0 Input Voltage | VIL | 0.8 | V | VCC = VBS = 12V | 5 | ||
| Enable Logic 1 Input Voltage | VENIH | 1.5 | V | 5 | |||
| Enable Logic 0 Input Voltage | VENIL | 0.7 | V | 5 | |||
| High Level Output Voltage, VBIAS - VO | VOH | 0.45 | 0.6 | V | IO+ = 100mA | 5 | |
| Low Level Output Voltage | VOL | 0.15 | 0.22 | V | IO- = 100mA | 5 | |
| Offset Supply Leakage Current | ILK | 10 | 50 | µA | VB = VS = 60V | 5 | |
| VCC Shutdown Supply Current | ICCSD | 0 | 1 | µA | VIN = 0V or 5V, VEN = 0V | 5 | |
| VCC Quiescent Supply Current | ICCQ | 0.28 | 0.5 | mA | VIN = 0V or 5V, RDT = 100kΩ | 5 | |
| VBS Quiescent Supply Current | IBSQ | 32 | 100 | µA | VIN = 0V or 5V | 5 | |
| Logic 1 Input Bias Current | IIN+ | 25 | 60 | µA | VIN = 5V | 5 | |
| Logic 0 Input Bias Current | IIN- | 0 | 1 | µA | VIN = 0V | 5 | |
| VBS Supply Undervoltage Positive Going Threshold | VBSUV+ | 3.3 | 3.8 | 4.2 | V | 5 | |
| VBS Supply Undervoltage Negative Going Threshold | VBSUV- | 2.9 | 3.3 | 3.9 | V | 5 | |
| VCC Supply Undervoltage Positive Going Threshold | VCCUV+ | 3.3 | 3.8 | 4.2 | V | 5 | |
| VCC Supply Undervoltage Negative Going Threshold | VCCUV- | 2.9 | 3.3 | 3.9 | V | 5 | |
| Output High Short-Circuit Pulsed Current | IO+ | 1 | 1.5 | A | VO = 0V, PW ≤ 10µs | 5 | |
| Output Low Short-Circuit Pulsed Current | IO- | 1.9 | 2.5 | A | VO = 15V, PW ≤ 10µs | 5 | |
| Turn-on Propagation Delay, HO & LO | tON | 65 | 96 | 125 | ns | RDT = 10kΩ | 5 |
| Turn-on Propagation Delay, HO & LO | tON | 350 | 463 | 580 | ns | RDT = 100kΩ | 5 |
| Turn-off Propagation Delay, HO & LO | tOFF | 22 | 56 | ns | 5 | ||
| Turn-on Rise Time | tr | 17 | 35 | ns | 5 | ||
| Turn-off Fall Time | tf | 12 | 25 | ns | 5 | ||
| Delay Matching | tDM | 50 | ns | 5 | |||
| Deadtime | tDT | 40 | 70 | 100 | ns | RDT = 10kΩ | 5 |
| Deadtime | tDT | 300 | 430 | 560 | ns | RDT = 100kΩ | 5 |
| Deadtime Matching | tMDT | 50 | ns | RDT = 100kΩ | 5 | ||
| High-Side Floating Positive Supply Voltage | VB | -0.3 | 60 | V | TA = +25°C | 4 | |
| Offset Supply Voltage Transient | dVS/dt | 50 | V/ns | TA = +25°C | 4 | ||
| Logic and Low-Side Fixed Supply Voltage | VCC | -0.3 | 14 | V | TA = +25°C | 4 | |
| Low-Side Output Voltage (lower bound; upper is VCC+0.3) | VLO | -0.3 | V | TA = +25°C | 4 | ||
| Logic Input Voltage (IN and EN) (lower bound; upper is VCC+0.3) | VIN | -0.3 | V | TA = +25°C | 4 | ||
| Power Dissipation Linear Derating Factor, MSOP-10 | PD | 0.75 | W | JEDEC 2-layer FR-4, minimum recommended pad layout | 4 | ||
| Thermal Resistance, Junction to Ambient, MSOP-10 | RθJA | 166 | °C/W | JEDEC 2-layer FR-4, minimum recommended pad layout | 4 | ||
| Thermal Resistance, Junction to Case, MSOP-10 | RθJC | 32 | °C/W | JEDEC 2-layer FR-4, minimum recommended pad layout | 4 | ||
| Operating Temperature (junction) | TJ | 150 | °C | 4 | |||
| Lead Temperature (Soldering, 10s) | TL | 300 | °C | 4 | |||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 4 | ||
| High-Side Floating Supply Offset Voltage | VS | 50 | V | Provided VB doesn't exceed 60V | 4 | ||
| Logic and Low-Side Fixed Supply Voltage | VCC | 4.5 | 14 | V | VCC = 4.5V to 4.9V needs external bootstrap Schottky diode | 4 | |
| Low-Side Output Voltage (lower bound; upper is VCC) | VLO | 0 | V | 4 | |||
| Logic Input Voltage (IN and EN) | VIN | 0 | 5 | V | 4 | ||
| Ambient Temperature | TA | -40 | 125 | °C | 4 | ||
| Input Voltage Hysteresis | VINHYS | 0.6 | V | 5 | |||
| VCC Operating Supply Current | ICCOP | 7.6 | mA | fs = 500kHz, CL = 1000pF | 5 | ||
| VBS Operating Supply Current | IBSOP | 7.6 | mA | fs = 500kHz, CL = 1000pF | 5 | ||
| Forward Voltage of Bootstrap Diode | VF1 | 0.67 | V | IF = 100µA | 5 | ||
| Forward Voltage of Bootstrap Diode | VF2 | 1.7 | V | IF = 100mA | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | • Terminals: Finish, Matte Tin Finish. Solderable per MIL-STD-202, Method 208 | 1 |
CAD (KiCad official)
- Symbol:
DGD05463M10-13 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
dgd05463m10-13-etched.step/dgd05463m10-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dgd05463m10-13.step/dgd05463m10-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (14 pp, sha256
8ef3358ed602ee43, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).