25LC160AT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS	input	Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode with SO in high impedance.
2	SO	tri_state	Serial Data Output: data is shifted out after the falling edge of the serial clock and goes high-impedance when the device is deselected or HOLD is low.
3	WP	input	Write-Protect: with WPEN set, WP low disables writes to the nonvolatile STATUS register bits; WP high allows normal operation.
4	VSS	power_in	Ground.
5	SI	input	Serial Data Input: receives instructions, addresses and data, latched on the rising edge of the serial clock.
6	SCK	input	Serial Clock Input: synchronizes communication, with SI latched on the rising edge and SO updated after the falling edge, max clock 10 MHz.
7	HOLD	input	Hold Input: pulling low while SCK is low pauses serial communication without resetting the sequence, and it must be held high when not used.
8	VCC	power_in	Supply Voltage: 2.5V to 5.5V for 25LC160A, absolute maximum 7.0V.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SOIC-8
Category	Single Chip Microcomputer/Microcontroller
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Supply voltage	VCC		7	V		2
Input/output voltage w.r.t. VSS		-0.6		V	All inputs and outputs, max is VCC +1.0V	2
Storage temperature		-65	150	°C		2
Ambient temperature under bias		-40	125	°C		2
ESD protection on all pins			4	kV		2
Supply voltage range	VCC	2.5	5.5	V	25LC160A	1
Operating ambient temperature (Industrial)	TAMB	-40	85	°C	Industrial (I)	2
High-level input voltage	VIH1	2		V	VCC ≥ 2.7V (max VCC +1)	2
Low-level input voltage	VIL1	-0.3	0.8	V	VCC ≥ 2.7V	2
Low-level input voltage	VIL2	-0.3		V	VCC < 2.7V (max 0.2 VCC)	2
Low-level output voltage	VOL		0.4	V	IOL = 2.1 mA	2
Input leakage current	ILI	-1	1	μA	CS = VCC, VIN = VSS TO VCC	2
Output leakage current	ILO	-1	1	μA	CS = VCC, VOUT = VSS TO VCC	2
Internal capacitance (all inputs and outputs)	CINT		7	pF	TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V	2
Read operating current	ICC Read		6	mA	VCC = 5.5V; FCLK = 10.0 MHz; SO = Open	2
Read operating current	ICC Read		2.5	mA	VCC = 2.5V; FCLK = 5.0 MHz; SO = Open	2
Write operating current	ICC Write		3	mA	VCC = 5.5V	2
Standby current	ICCS		5	μA	CS = VCC = 5.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +125°C	2
Standby current	ICCS		1	μA	CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C	2
Clock frequency	FCLK		10	MHz	4.5V ≤ VCC ≤ 5.5V	3
Clock frequency	FCLK		5	MHz	2.5V ≤ VCC < 4.5V	3
CS setup time	TCSS	50		ns	4.5V ≤ VCC ≤ 5.5V	3
CS setup time	TCSS	100		ns	2.5V ≤ VCC < 4.5V	3
CS hold time	TCSH	100		ns	4.5V ≤ VCC ≤ 5.5V	3
CS hold time	TCSH	200		ns	2.5V ≤ VCC < 4.5V	3
CS disable time	TCSD	50		ns		3
Data setup time	Tsu	10		ns	4.5V ≤ VCC ≤ 5.5V	3
Data setup time	Tsu	20		ns	2.5V ≤ VCC < 4.5V	3
Data hold time	THD	20		ns	4.5V ≤ VCC ≤ 5.5V	3
Data hold time	THD	40		ns	2.5V ≤ VCC < 4.5V	3
CLK rise time	TR		500	ns	Note 1	3
CLK fall time	TF		500	ns	Note 1	3
Clock high time	THI	50		ns	4.5V ≤ VCC ≤ 5.5V	3
Clock high time	THI	100		ns	2.5V ≤ VCC < 4.5V	3
Clock low time	TLO	50		ns	4.5V ≤ VCC ≤ 5.5V	3
Clock low time	TLO	100		ns	2.5V ≤ VCC < 4.5V	3
Clock delay time	TCLD	50		ns		3
Clock enable time	TCLE	50		ns		3
Output valid from clock low	TV		50	ns	4.5V ≤ VCC ≤ 5.5V	3
Output valid from clock low	TV		100	ns	2.5V ≤ VCC < 4.5V	3
Output hold time	THO	0		ns	Note 1	3
Output disable time	TDIS		40	ns	4.5V ≤ VCC ≤ 5.5V (Note 1)	3
Output disable time	TDIS		80	ns	2.5V ≤ VCC ≤ 4.5V (Note 1)	3
HOLD setup time	THS	20		ns	4.5V ≤ VCC ≤ 5.5V	3
HOLD setup time	THS	40		ns	2.5V ≤ VCC < 4.5V	3
HOLD hold time	THH	20		ns	4.5V ≤ VCC ≤ 5.5V	4
HOLD hold time	THH	40		ns	2.5V ≤ VCC < 4.5V	4
HOLD low to output high-Z	THZ	30		ns	4.5V ≤ VCC ≤ 5.5V (Note 1)	4
HOLD low to output high-Z	THZ	60		ns	2.5V ≤ VCC < 4.5V (Note 1)	4
HOLD high to output valid	THV	30		ns	4.5V ≤ VCC ≤ 5.5V	4
HOLD high to output valid	THV	60		ns	2.5V ≤ VCC < 4.5V	4
Internal write cycle time	TWC		5	ms	NOTE 3	4

CAD (KiCad official)

Symbol: 25LC160AT-I
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: 25lc160at-i-etched.step / 25lc160at-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25lc160at-i.step / 25lc160at-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (26 pp, sha256 47632048a5bb7e60, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

25LC160AT-I

Verified 25LC160AT-I

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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