component
BQ24707ARGRT
Public Made by Adomby adom
Texas Instruments Battery Management ICs, VQFN-20-EP(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownBQ24707ARGRT
Texas Instruments · Battery Management ICs · VQFN-20-EP(3.5x3.5)
BQ24707ARGRT from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ACN | input | Input current-sense resistor negative input; place an optional 0.1-µF ceramic capacitor from ACN to GND for common-mode filtering and 0.1 µF from ACN to ACP for differential-mode filtering. |
| 2 | ACP | input | Input current-sense resistor positive input; place a 0.1-µF ceramic capacitor from ACP to GND for common-mode filtering and 0.1 µF from ACN to ACP for differential-mode filtering. |
| 3 | CMPOUT | output | Open-drain output of the independent comparator with 0.6 V or 2.4 V internal reference selectable by ChargeOption(); goes HIGH when CMPIN is above the reference; use a 10-kΩ pullup. |
| 4 | CMPIN | input | Independent comparator input with a 50-kΩ series resistor and 2000-kΩ pulldown, compared against a 0.6 V or 2.4 V internal reference selected by ChargeOption(); CMPOUT goes HIGH when CMPIN is above the reference. |
| 5 | ACOK | output | AC adapter detect open-drain output, pulled LOW when ACDET is above 2.4 V, VCC is above UVLO and VCC is 245 mV above SRN; requires a 10-kΩ pullup. |
| 6 | ACDET | input | Adapter detection input programmed by a resistor divider from the adapter input to GND; above 0.6 V with VCC above UVLO enables the REGN LDO, ACOK comparator and IOUT. |
| 7 | IOUT | output | Buffered adapter or charge current output selectable by ChargeOption(), with voltage equal to 20 times the sense-resistor differential voltage; place 100 pF or less decoupling capacitor to GND. |
| 8 | SDA | bidirectional | SMBus open-drain data I/O connected to the host or smart battery data line with a 10-kΩ pullup. |
| 9 | SCL | input | SMBus open-drain clock input connected to the host or smart battery clock line with a 10-kΩ pullup. |
| 10 | ILIM | input | Charge current-limit input programmed by a divider from the 3.3-V rail; the lower of ILIM or DAC limit sets the limit, control is disabled above 1.6 V, charge is disabled below 75 mV and enabled above 105 mV. |
| 11 | IFAULT | output | Open-drain output pulled LOW by an internal MOSFET when ACOC or a short-circuit is detected, otherwise pulled HIGH by an external pullup. |
| 12 | SRN | input | Charge current-sense resistor negative input and battery voltage sensing pin; connect through a 7.5-Ω resistor with a 0.1-µF capacitor to GND for common-mode filtering. |
| 13 | SRP | input | Charge current-sense resistor positive input; connect through a 10-Ω resistor to the current-sensing resistor with a 0.1-µF capacitor for differential-mode filtering. |
| 14 | GND | power_in | IC ground; connect to the analog ground plane and only to the power ground plane through the PowerPAD underneath the IC. |
| 15 | LODRV | output | Low-side power MOSFET driver output connected to the low-side N-channel MOSFET gate. |
| 16 | REGN | power_out | Output of the 6-V linear regulator supplied from VCC, active when ACDET is above 0.6 V and VCC is above UVLO; connect a 1-µF ceramic capacitor to GND. |
| 17 | BTST | power_in | High-side power MOSFET driver power supply; connect a 0.047-µF capacitor from BTST to PHASE and a bootstrap Schottky diode from REGN to BTST. |
| 18 | HIDRV | output | High-side power MOSFET driver output connected to the high-side N-channel MOSFET gate. |
| 19 | PHASE | passive | High-side power MOSFET driver source connected to the source of the high-side N-channel MOSFET. |
| 20 | VCC | power_in | Input supply, diode OR from adapter or battery voltage; use a 10-Ω resistor and 1-µF capacitor to ground as a low-pass filter to limit inrush current. |
| 21 | PowerPAD | power_in | Exposed pad beneath the IC, analog and power ground star-connected only at the PowerPAD plane; always solder to the board with vias to ground planes; also serves as thermal pad. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(3.5x3.5) |
| Category | Power Supply Chip |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on SRN, SRP, ACN, ACP, VCC | -0.3 | 30 | V | 5 | |||
| Voltage on PHASE | -2 | 30 | V | 5 | |||
| Voltage on ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK, IFAULT, CMPIN, CMPOUT | -0.3 | 7 | V | 5 | |||
| Voltage on BTST, HIDRV | -0.3 | 36 | V | 5 | |||
| Maximum difference voltage SRP-SRN, ACP-ACN | -0.5 | 0.5 | V | 5 | |||
| Junction temperature | TJ | -40 | 155 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 155 | °C | 5 | ||
| Voltage on SRN, SRP, ACN, ACP, VCC | 0 | 24 | V | 5 | |||
| Voltage on PHASE | -2 | 24 | V | 5 | |||
| Voltage on ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK, IFAULT, CMPIN, CMPOUT | 0 | 6.5 | V | 5 | |||
| Voltage on BTST, HIDRV | 0 | 30 | V | 5 | |||
| Maximum difference voltage SRP-SRN, ACP-ACN | -0.2 | 0.2 | V | 5 | |||
| Junction temperature | TJ | 0 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 46.8 | °C/W | RGR 20-pin VQFN | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.4 | °C/W | RGR 20-pin VQFN | 5 | ||
| VCC input voltage operating | VVCC_OP | 4.5 | 24 | V | 6 | ||
| BAT voltage regulation range | VBAT_REG_RNG | 1.024 | 19.2 | V | 6 | ||
| Charge voltage regulation accuracy | VBAT_REG_ACC | 16.716 | 16.8 | 16.884 | V | ChargeVoltage() = 0x41A0H | 6 |
| Charge voltage regulation accuracy tolerance | VBAT_REG_ACC | -0.5 | 0.5 | % | ChargeVoltage() = 0x41A0H | 6 | |
| Charge current regulation accuracy | ICHRG_REG_ACC | 3973 | 4096 | 4219 | mA | ChargeCurrent() = 0x1000H | 6 |
| Input current regulation accuracy | IDPM_REG_ACC | 3973 | 4096 | 4219 | mA | InputCurrent() = 0x1000H | 6 |
| Charge current regulation differential voltage | VIREG_CHG_RNG | 0 | 81.28 | mV | VIREG_CHG = VSRP - VSRN | 6 | |
| Input current regulation differential voltage | VIREG_DPM_RNG | 0 | 80.64 | mV | VIREG_DPM = VACP - VACN | 6 | |
| Input common mode voltage on ACP/ACN | VACP/N_OP | 4.5 | 24 | V | 6 | ||
| Output common mode voltage on SRP/SRN | VSRP/N_OP | 0 | 19.2 | V | 6 | ||
| IOUT output voltage | VIOUT | 0 | 1.6 | V | 6 | ||
| IOUT output current | IIOUT | 0 | 1 | mA | 6 | ||
| Maximum output load capacitance | CIOUT_MAX | 100 | pF | For stability with 0- to 1-mA load | 7 | ||
| REGN regulator voltage | VREGN_REG | 5.5 | 6 | 6.5 | V | VVCC > 6.5 V, VACDET > 0.6 V, 0-55 mA load | 7 |
| REGN current limit, charge enabled and not in TSHUT | IREGN_LIM | 65 | 80 | mA | VREGN = 0 V, VVCC > UVLO | 7 | |
| REGN current limit, charge disabled or in TSHUT | IREGN_LIM_TSHUT | 7 | 16 | mA | VREGN = 0 V, VVCC > UVLO | 7 | |
| Input undervoltage rising threshold | VUVLO | 3.5 | 3.75 | 4 | V | VVCC rising | 7 |
| Total battery leakage current | IBAT | 15 | µA | VVCC < VBAT = 16.8 V, TJ = 0 to 85°C | 7 | ||
| Standby quiescent current | ISTANDBY | 0.5 | 1 | mA | VVCC > VUVLO, VACDET > 0.6 V, charge disabled, TJ = 0 to 85°C | 7 | |
| Adapter bias current during charge, no switching | IAC_NOSW | 1.5 | 3 | mA | VVCC > VUVLO, VACDET > 2.4 V, charge enabled, no switching, TJ = 0 to 85°C | 7 | |
| ACOK falling threshold | VACOK_FALL | 2.376 | 2.4 | 2.424 | V | VVCC>VUVLO, VACDET rising | 7 |
| ACOK rising hysteresis | VACOK_RISE_HYS | 35 | 55 | 75 | mV | VVCC>VUVLO, VACDET falling | 7 |
| VCC-SRN falling threshold | VVCC-SRN_FALL | 70 | 125 | 180 | mV | VVCC falling towards VSRN | 7 |
| High-side IFAULT comparator rising threshold, default | VIFAULT_HI_RISE | 450 | 700 | 1000 | mV | ChargeOption() bit [8:7] = 10 (default), ACP to PHASE | 8 |
| Low-side IFAULT comparator rising threshold | VIFAULT_LOW_RISE | 40 | 110 | 160 | mV | PHASE to GND | 8 |
| Adapter overcurrent rising threshold, default | VACOC | 150 | 166 | 180 | % | ChargeOption() bit [2:1] = 10 (default), with respect to input current limit | 8 |
| ACOC deglitch time | tACOC_DEG | 1.7 | 2.5 | 3.3 | ms | Voltage across input sense resistor rising to disable charge | 8 |
| Overvoltage rising threshold as percentage of VBAT_REG | VOVP_RISE | 103 | 104 | 106 | % | VSRN rising | 8 |
| Charge overcurrent rising threshold | VOCP_RISE | 54 | 60 | 66 | mV | ChargeCurrent() = 0x0xxxH | 8 |
| Charge overcurrent rising threshold | VOCP_RISE | 80 | 90 | 100 | mV | ChargeCurrent() = 0x1000H - 0x17C0H | 8 |
| Charge overcurrent rising threshold | VOCP_RISE | 110 | 120 | 130 | mV | ChargeCurrent() = 0x1800H - 0x1FC0H | 8 |
| Charge undercurrent falling threshold | VUCP_FALL | 1 | 5 | 9 | mV | VSRP falling towards VSRN | 8 |
| Battery LOWV falling threshold | VBATLV_FALL | 2.4 | 2.5 | 2.6 | V | VSRN falling | 8 |
| Battery LOWV charge current limit | IBATLV | 0.5 | A | 10-mΩ current sensing resistor | 8 | ||
| ILIM as CE falling threshold | VILIM_FALL | 60 | 75 | 90 | mV | VILIM falling | 9 |
| ILIM as CE rising threshold | VILIM_RISE | 90 | 105 | 120 | mV | VILIM rising | 9 |
| Input low threshold | VIN_LO | 0.8 | V | SDA, SCL | 9 | ||
| Input high threshold | VIN_HI | 2.1 | V | SDA, SCL | 9 | ||
| Output saturation voltage | VOUT_LO | 500 | mV | 5-mA drain current, ACOK, SDA, IFAULT, CMPOUT | 9 | ||
| PWM switching frequency, default | FSW | 600 | 750 | 900 | kHz | ChargeOption() bit [9] = 0 (default) | 9 |
| PWM increase frequency | FSW+ | 665 | 885 | 1100 | kHz | ChargeOption() bit [10:9] = 11 | 9 |
| PWM decrease frequency | FSW- | 465 | 615 | 765 | kHz | ChargeOption() bit [10:9] = 01 | 9 |
| Comparator reference, default | VIC_REF1 | 0.585 | 0.6 | 0.615 | V | ChargeOption() bit [4] = 0, rising edge (default) | 9 |
| ACOK falling deglitch, bq24707A | tACOK_FALL_DEG | 0.8 | 1.2 | 2 | ms | VVCC>VUVLO, VACDET rising above 2.4 V, ChargeOption() bit [15] = 0 (default), bq24707A only | 10 |
| ACOK falling deglitch, bit 15 = 1 | tACOK_FALL_DEG | 10 | 50 | µs | VVCC>VUVLO, VACDET rising above 2.4 V, ChargeOption() bit [15] = 1 | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3. Place inductor input terminal to the output terminal of the switching MOSFET as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make | 31 |
CAD (KiCad official)
- Symbol:
BQ24707ARGRT - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: VQFN-20-EP(3.5x3.5) (KiCad packages3D, STEP)
- 3D model files:
bq24707argrt-etched.step/bq24707argrt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24707argrt.step/bq24707argrt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
cc2349aa2dc03010, retrieved 2026-11-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).