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MSP430FR5964IPNR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MSP430FR5964IPNR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430FR5964IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA0.1, DMAE0, RTCCLK, A0, C0, VREF- and VeREF-.
2 P1.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA0.2, TA1CLK, COUT, A1, C1, VREF+ and VeREF+.
3 P1.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA1.1, TA0CLK, COUT, A2 and C2.
4 P3.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A12 and comparator input C12.
5 P3.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A13 and comparator input C13.
6 P3.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A14 and comparator input C14.
7 P3.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A15 and comparator input C15.
8 P6.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_A3 UCA3TXD/UCA3SIMO.
9 P6.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_A3 UCA3RXD/UCA3SOMI.
10 P6.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_A3 clock UCA3CLK.
11 P6.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_A3 slave transmit enable UCA3STE.
12 P4.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
13 P7.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B2 UCB2SIMO/UCB2SDA.
14 P7.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B2 UCB2SOMI/UCB2SCL.
15 P8.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
16 P1.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA1.2, UCB0STE, A3 and C3.
17 P1.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.1, UCA0STE, A4 and C4.
18 P1.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.2, UCA0CLK, A5 and C5.
19 DVSS2 power_in Digital ground supply.
20 DVCC2 power_in Digital power supply; supply range is 1.8 V to 3.6 V at all DVCC and AVCC pins.
21 PJ.0 bidirectional General-purpose digital I/O shared with JTAG TDO, TB0OUTH, SMCLK, SRSCG1 and comparator input C6.
22 PJ.1 bidirectional General-purpose digital I/O shared with JTAG TDI/TCLK, MCLK, SRSCG0 and comparator input C7.
23 PJ.2 bidirectional General-purpose digital I/O shared with JTAG TMS, ACLK, SROSCOFF and comparator input C8.
24 PJ.3 bidirectional General-purpose digital I/O shared with JTAG TCK, SRCPUOFF and comparator input C9.
25 P7.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B2 clock UCB2CLK.
26 P7.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with UCB2STE and TA4.1.
27 P7.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA4.0 and ADC input A16.
28 P7.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A17.
29 P7.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A18.
30 P7.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A19.
31 P4.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A8.
32 P4.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A9.
33 P4.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A10.
34 P4.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with ADC input A11.
35 P2.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO.
36 P2.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI.
37 TEST/SBWTCK input Test mode pin that selects digital I/O on JTAG pins and serves as Spy-Bi-Wire input clock; has an internal pulldown always enabled.
38 RST/NMI/SBWTDIO bidirectional Active-low reset input, nonmaskable interrupt input and Spy-Bi-Wire data input/output; unused connection is DVCC or VCC via 47-kΩ pullup or internal pullup with 10-nF (2.2 nF for Spy-Bi-Wire) pulldown.
39 DVSS3 power_in Digital ground supply.
40 DVCC3 power_in Digital power supply; supply range is 1.8 V to 3.6 V at all DVCC and AVCC pins.
41 P2.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.6, UCA0TXD/UCA0SIMO, TB0CLK, ACLK and UART BSLTX.
42 P2.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.0, UCA0RXD/UCA0SOMI and UART BSLRX.
43 P2.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.2 and eUSCI_B0 clock UCB0CLK.
44 P8.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
45 P8.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
46 P8.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
47 P3.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.3 and SMCLK output.
48 P3.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.4 and COUT.
49 P3.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.5.
50 P3.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.6.
51 P1.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.3, UCB0SIMO/UCB0SDA, TA0.0 and I2C BSL data BSLSDA.
52 P1.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.4, UCB0SOMI/UCB0SCL, TA1.0 and I2C BSL clock BSLSCL.
53 P5.0 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B1 UCB1SIMO/UCB1SDA.
54 P5.1 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B1 UCB1SOMI/UCB1SCL.
55 P5.2 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B1 clock UCB1CLK and TA4CLK.
56 P5.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B1 slave transmit enable UCB1STE.
57 P4.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TB0.5.
58 P4.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
59 P4.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
60 DVSS1 power_in Digital ground supply.
61 DVCC1 power_in Digital power supply; supply range is 1.8 V to 3.6 V at all DVCC and AVCC pins.
62 P2.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5.
63 P2.3 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA0.0, UCA1STE, ADC input A6 and comparator input C10.
64 P2.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with TA1.0, UCA1CLK, ADC input A7 and comparator input C11.
65 P5.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with UCA2TXD/UCA2SIMO and TB0OUTH.
66 P5.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with UCA2RXD/UCA2SOMI and ACLK output.
67 P5.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with UCA2CLK, TA4.0 and SMCLK output.
68 P5.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with UCA2STE, TA4.1 and MCLK output.
69 P6.4 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B3 UCB3SIMO/UCB3SDA.
70 P6.5 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B3 UCB3SOMI/UCB3SCL.
71 P6.6 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B3 clock UCB3CLK.
72 P6.7 bidirectional General-purpose digital I/O with port interrupt and wake up from LPMx.5, shared with eUSCI_B3 slave transmit enable UCB3STE.
73 AVSS3 power_in Analog ground supply.
74 PJ.6/HFXIN bidirectional General-purpose digital I/O and input for high-frequency crystal oscillator HFXT.
75 PJ.7/HFXOUT bidirectional General-purpose digital I/O and output for high-frequency crystal oscillator HFXT.
76 AVSS2 power_in Analog ground supply.
77 PJ.4/LFXIN bidirectional General-purpose digital I/O and input for low-frequency crystal oscillator LFXT.
78 PJ.5/LFXOUT bidirectional General-purpose digital I/O and output of low-frequency crystal oscillator LFXT.
79 AVSS1 power_in Analog ground supply.
80 AVCC1 power_in Analog power supply; supply range is 1.8 V to 3.6 V at all DVCC and AVCC pins, with 1 µF plus 100 nF decoupling recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430FR5964IPNR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430fr5964ipnr-etched.step / msp430fr5964ipnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr5964ipnr.step / msp430fr5964ipnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (177 pp, sha256 305369231542d625, retrieved 2026-09-30, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF