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Contents

README

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TF60N04

TF · MOSFETs · TO-252

TF60N04 from TF, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; gate-source voltage limited to ±20 V, with a threshold voltage VGS(TH) of 1.0 V min and 2.3 V typ at ID=250 µA.
2 D passive Drain (center lead, electrically common with the drain tab); VDS max 40 V and continuous ID 60 A at TC=25 °C.
3 S passive Source; carries the 60 A continuous drain current at TC=25 °C (pulsed IDM 150 A).

Key specifications

Parameter Value
Manufacturer TF
Package TO-252
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 40 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 60 A TC=25℃ 1
Continuous Drain Current ID 42 A TC=75℃ 1
Continuous Drain Current ID 36 A TC=100℃ 1
Pulsed Drain Current IDM 150 A Pulse width ≤ 300μs, Duty cycle ≤ 2% 1
Total Power Dissipation PD 55 W TC=25℃ 1
Total Power Dissipation PD 2 W TA=25℃ 1
Operating Junction Temperature TJ -55 150 ℃ 1
Storage Temperature TSTG -55 150 ℃ 1
Single Pulse Avalanche Energy EAS 120 mJ 2
Avalanche Current IAS 30 A 2
Thermal resistance, junction - case RthJC 2 °C/W 2
Thermal resistance, junction - ambient RthJA 55 °C/W 2
Soldering temperature, wave soldering Tsold 265 °C 8s 2
Drain-Source Breakdown Voltage BVDSS 40 V VGS=0V, ID=250uA 2
Gate Threshold Voltage VGS(TH) 1 2.3 V VGS=VDS, ID=250uA 2
Drain-Source Leakage Current IDSS 1 uA VDS=40V, VGS=0V 2
Gate-Source Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 2
Static Drain-source On Resistance RDS(ON) 6.5 8.5 mΩ VGS=10V, ID=20A 2
Static Drain-source On Resistance RDS(ON) 9 12 mΩ VGS=4.5V, ID=20A 2
Source-drain voltage VSD 1.2 V Is=20A 2
Forward Transconductance gFS 15 S VDS=15V, ID=20A 2
Input capacitance Ciss 1235 pF Vds=20V, Vgs=0V, f = 1MHz 2
Output capacitance Coss 152.5 pF Vds=20V, Vgs=0V, f = 1MHz 2
Reverse transfer capacitance Crss 138.5 pF Vds=20V, Vgs=0V, f = 1MHz 2
Gate Resistance Rg 1.5 Ω f = 1MHz 2
Total gate charge Qg 25.5 nC VDD = 20V, ID = 20A, VGS = 10V 2
Gate - Source charge Qgs 3.2 nC VDD = 20V, ID = 20A, VGS = 10V 2
Gate - Drain charge Qgd 6.5 nC VDD = 20V, ID = 20A, VGS = 10V 2
Turn-ON Delay time tD(on) 8 ns VGS=10V, VDS=20V, RG=2.7Ω, ID=20A 2
Turn-ON Rise time tr 17.8 ns VGS=10V, VDS=20V, RG=2.7Ω, ID=20A 2
Turn-Off Delay time tD(off) 120 ns VGS=10V, VDS=20V, RG=2.7Ω, ID=20A 2
Turn-Off Fall time tf 70 ns VGS=10V, VDS=20V, RG=2.7Ω, ID=20A 2

CAD (KiCad official)

  • Symbol: TF60N04
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: tf60n04-etched.step / tf60n04-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tf60n04.step / tf60n04.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TF datasheet (6 pp, sha256 d448f78ad0132ed2, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF