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TMS320F28016PZA

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F28016PZA

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28016PZA from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12/TZ1 bidirectional General-purpose I/O 12 with pullup enabled at reset; alternate function is Trip Zone input 1 (I).
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin, 3.3 V.
4 GPIO29/SCITXDA/TZ6 bidirectional General-purpose I/O 29 with 8-mA (typical) output buffer; alternate functions are SCI-A transmit data (O) and Trip Zone 6 input (I).
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (I/O/Z); alternate functions are I2C clock open-drain port, EPWM external sync output and ADC SOC B output.
6 GPIO30/CANRXA bidirectional General-purpose I/O 30 with 8-mA (typical) output buffer; alternate function is eCAN-A receive data (I). Not applicable on TMS320F28015, but available on F28016.
7 GPIO31/CANTXA bidirectional General-purpose I/O 31 with 8-mA (typical) output buffer; alternate function is eCAN-A transmit data (O). Not applicable on TMS320F28015, but available on F28016.
8 GPIO14/TZ3 bidirectional General-purpose I/O 14 with pullup enabled at reset; alternate function is Trip Zone input 3 (I).
9 GPIO15/TZ4 bidirectional General-purpose I/O 15 with pullup enabled at reset; alternate function is Trip Zone input 4 (I).
10 VDD power_in CPU and logic digital power pin, 1.8 V.
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin, 1.8 V.
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin, 3.3 V.
16 ADCINA7 passive ADC Group A, channel 7 analog input, 0 to 3 V with respect to ADCLO.
17 ADCINA6 passive ADC Group A, channel 6 analog input, 0 to 3 V with respect to ADCLO.
18 ADCINA5 passive ADC Group A, channel 5 analog input, 0 to 3 V with respect to ADCLO.
19 ADCINA4 passive ADC Group A, channel 4 analog input, 0 to 3 V with respect to ADCLO.
20 ADCINA3 passive ADC Group A, channel 3 analog input, 0 to 3 V with respect to ADCLO.
21 ADCINA2 passive ADC Group A, channel 2 analog input, 0 to 3 V with respect to ADCLO.
22 ADCINA1 passive ADC Group A, channel 1 analog input, 0 to 3 V with respect to ADCLO.
23 ADCINA0 passive ADC Group A, channel 0 analog input, 0 to 3 V with respect to ADCLO.
24 ADCLO input ADC low reference; connect to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin, 3.3 V.
27 ADCINB0 passive ADC Group B, channel 0 analog input, 0 to 3 V with respect to ADCLO.
28 ADCINB1 passive ADC Group B, channel 1 analog input, 0 to 3 V with respect to ADCLO.
29 ADCINB2 passive ADC Group B, channel 2 analog input, 0 to 3 V with respect to ADCLO.
30 ADCINB3 passive ADC Group B, channel 3 analog input, 0 to 3 V with respect to ADCLO.
31 ADCINB4 passive ADC Group B, channel 4 analog input, 0 to 3 V with respect to ADCLO.
32 ADCINB5 passive ADC Group B, channel 5 analog input, 0 to 3 V with respect to ADCLO.
33 ADCINB6 passive ADC Group B, channel 6 analog input, 0 to 3 V with respect to ADCLO.
34 ADCINB7 passive ADC Group B, channel 7 analog input, 0 to 3 V with respect to ADCLO.
35 ADCREFIN input External ADC reference input; connect to VSS when the internal reference is used.
36 ADCREFM output ADC internal reference medium output; requires a 2.2 uF ceramic bypass capacitor with ESR under 1.5 ohm to analog ground and must not be loaded externally.
37 ADCREFP output ADC internal reference positive output; requires a 2.2 uF ceramic bypass capacitor with ESR under 1.5 ohm to analog ground and must not be loaded externally.
38 ADCRESEXT passive ADC external current bias resistor; connect a 22-kohm resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin, 1.8 V.
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin, 1.8 V.
43 GPIO34 bidirectional General-purpose I/O 34 (I/O/Z) with no alternate function listed in this package table.
44 GPIO1/EPWM1B bidirectional General-purpose I/O 1 with pullup not enabled at reset; alternate function is Enhanced PWM1 output B (O).
45 GPIO2/EPWM2A bidirectional General-purpose I/O 2 with pullup not enabled at reset; alternate function is Enhanced PWM2 output A and HRPWM channel (O).
46 VDDIO power_in Digital I/O power pin, 3.3 V.
47 GPIO0/EPWM1A bidirectional General-purpose I/O 0 with pullup not enabled at reset; alternate function is Enhanced PWM1 output A and HRPWM channel (O).
48 GPIO3/EPWM2B bidirectional General-purpose I/O 3 with pullup not enabled at reset; alternate function is Enhanced PWM2 output B (O).
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/TZ5 bidirectional General-purpose I/O 16 with pullup enabled at reset; alternate function is SPI-A slave in / master out (I/O), with Trip Zone 5 input (I) also available on the F2801x pin list.
51 GPIO4/EPWM3A bidirectional General-purpose I/O 4 with pullup not enabled at reset; alternate function is Enhanced PWM3 output A and HRPWM channel (O).
52 GPIO17/SPISOMIA/TZ6 bidirectional General-purpose I/O 17 with pullup enabled at reset; alternate functions are SPI-A slave out / master in (I/O) and Trip Zone 6 input (I).
53 GPIO5/EPWM3B/ECAP1 bidirectional General-purpose I/O 5 with pullup not enabled at reset; alternate functions are Enhanced PWM3 output B (O) and Enhanced capture 1 (I/O).
54 GPIO18/SPICLKA bidirectional General-purpose I/O 18 with pullup enabled at reset; alternate function is SPI-A clock input/output (I/O).
55 VSS power_in Digital ground pin.
56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 with pullup enabled at reset; alternate functions are Enhanced PWM4 output A (O), external ePWM sync input (I) and external ePWM sync output (O).
57 GPIO19/SPISTEA bidirectional General-purpose I/O 19 with pullup enabled at reset; alternate function is SPI-A slave transmit enable input/output (I/O).
58 GPIO7/EPWM4B/ECAP2 bidirectional General-purpose I/O 7 with pullup not enabled at reset; alternate functions are Enhanced PWM4 output B (O) and Enhanced capture 2 (I/O).
59 VDD power_in CPU and logic digital power pin, 1.8 V.
60 GPIO8/ADCSOCAO bidirectional General-purpose I/O 8 with pullup not enabled at reset; alternate function is ADC start-of-conversion A output (O).
61 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose I/O 9 with pullup not enabled at reset; alternate functions are Enhanced PWM5 output B (O), SCI-B transmit (O) and Enhanced capture 3 (I/O).
62 VSS power_in Digital ground pin.
63 GPIO20/EQEP1A bidirectional General-purpose I/O 20 with pullup enabled at reset; alternate function is Enhanced QEP1 input A (I).
64 GPIO10/ADCSOCBO bidirectional General-purpose I/O 10 with pullup not enabled at reset; alternate function is ADC start-of-conversion B output (O).
65 VDDIO power_in Digital I/O power pin, 3.3 V.
66 XCLKOUT tri_state Output clock derived from SYSCLKOUT (same, one-half or one-quarter frequency, set by XCLKOUTDIV); not placed in high-impedance state during reset, 8-mA drive.
67 GPIO21/EQEP1B bidirectional General-purpose I/O 21 with pullup enabled at reset; alternate function is Enhanced QEP1 input B (I).
68 VDD power_in CPU and logic digital power pin, 1.8 V.
69 VSS power_in Digital ground pin.
70 GPIO11/EPWM6B/SCIRXDB/ECAP4 bidirectional General-purpose I/O 11 with pullup not enabled at reset; alternate functions are Enhanced PWM6 output B (O), SCI-B receive (I) and Enhanced capture 4 (I/O).
71 GPIO22/EQEP1S bidirectional General-purpose I/O 22 with pullup enabled at reset; alternate function is Enhanced QEP1 strobe (I/O).
72 GPIO23/EQEP1I bidirectional General-purpose I/O 23 with pullup enabled at reset; alternate function is Enhanced QEP1 index (I/O).
73 TDI input JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK.
74 TMS input JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
75 TCK input JTAG test clock with internal pullup.
76 TDO tri_state JTAG scan out test data output, shifted out on the falling edge of TCK with 8-mA drive.
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal pullup, driven low for 512 OSCCLK cycles during watchdog reset.
79 GPIO27/ECAP4/EQEP2S/SPISTEB bidirectional General-purpose I/O 27 with pullup enabled at reset; alternate functions are Enhanced capture 4 and Enhanced QEP2 strobe (I/O), and SPI-B slave transmit enable (I/O). Some functions are not available on F2801x.
80 EMU0 bidirectional Emulator pin 0 (I/O/Z, 8-mA drive, pullup); an external pullup of 2.2 kohm to 4.7 kohm is recommended.
81 EMU1 bidirectional Emulator pin 1 (I/O/Z, 8-mA drive, pullup); an external pullup of 2.2 kohm to 4.7 kohm is recommended.
82 VDDIO power_in Digital I/O power pin, 3.3 V.
83 GPIO24/ECAP1 bidirectional General-purpose I/O 24 with pullup enabled at reset; alternate function is Enhanced capture 1 (I/O).
84 TRST input JTAG test reset with internal pulldown; must be held low during normal operation and requires an external pulldown (2.2 kohm generally adequate); do not use pullup.
85 VDD power_in CPU and logic digital power pin, 1.8 V.
86 X2 output Internal oscillator output; quartz crystal or ceramic resonator connects across X1 and X2; leave unconnected if not used.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input referenced to the 1.8 V core supply; 1.8 V external oscillator may be fed here with XCLKIN tied to ground.
89 VSS power_in Digital ground pin.
90 XCLKIN input External oscillator input for a 3.3 V clock; tie X1 to GND in that case, or tie XCLKIN to GND when a crystal or 1.8 V oscillator on X1 is used.
91 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose I/O 25 with pullup enabled at reset; alternate functions are Enhanced capture 2 (I/O), Enhanced QEP2 input B (I, not on 2801/2802) and SPI-B master in / slave out (I/O).
92 GPIO28/SCIRXDA/TZ5 bidirectional General-purpose I/O 28 with 8-mA (typical) output buffer and pullup enabled at reset; alternate functions are SCI-A receive data (I) and Trip Zone 5 input (I).
93 VDD power_in CPU and logic digital power pin, 1.8 V.
94 VSS power_in Digital ground pin.
95 GPIO13/TZ2 bidirectional General-purpose I/O 13 with pullup enabled at reset; alternate function is Trip Zone input 2 (I).
96 VDD3VFL power_in 3.3 V flash core power pin; must be connected to 3.3 V at all times.
97 TEST1 unconnected Reserved for TI test; must be left unconnected.
98 TEST2 unconnected Reserved for TI test; must be left unconnected.
99 GPIO26/ECAP3/EQEP2I/SPICLKB bidirectional General-purpose I/O 26 with pullup enabled at reset; alternate functions are Enhanced capture 3, Enhanced QEP2 index and SPI-B clock (I/O); some are not available on F2801x.
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 with pullup enabled at reset; alternate functions are I2C data open-drain port (I/OD), external ePWM sync input (I) and ADC SOC A output (O).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28016PZA
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28016pza-etched.step / tms320f28016pza-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28016pza.step / tms320f28016pza.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF