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STM32H755ZIT6
Public Made by Adomby adom
STMicroelectronics Global Sourcing Parts, LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32H755ZIT6
STMicroelectronics · Global Sourcing Parts · LQFP-144(20x20)
STM32H755ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACECLK, SAI1_CK1, SPI4_SCK, QUADSPI_BK1_IO2 and FMC_A23. |
| 2 | PE3 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED0, TIM15_BKIN, SAI1_SD_B and FMC_A19. |
| 3 | PE4 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED1, SAI1_D2, DFSDM1_DATIN3, SPI4_NSS and DCMI_D4. |
| 4 | PE5 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED2, SAI1_CK2, SPI4_MISO, FMC_A21 and DCMI_D6. |
| 5 | PE6 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED3, TIM1_BKIN2, SAI1_D1, SPI4_MOSI and FMC_A22. |
| 6 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 7 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 8 | VBAT | power_in | Backup-domain supply input, specified at 1.2 to 3.6 V VBAT supply, also supporting battery charging. |
| 9 | PC13 | bidirectional | 5 V-tolerant I/O (FT) with EVENTOUT function and additional RTC_TAMP1/RTC_TS/WKUP2 functions. |
| 10 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O (FT) that also serves as OSC32_IN; when configured as oscillator the function is kept during and after reset except power-on reset. |
| 11 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O (FT) that also serves as OSC32_OUT; when configured as oscillator the function is kept during and after reset except power-on reset. |
| 12 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 13 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 14 | VSSSMPS | power_in | Ground pin dedicated to the SMPS step-down converter. |
| 15 | VLXSMPS | power_out | Switching node of the SMPS step-down converter, which directly supplies VCORE and/or external circuitry. |
| 16 | VDDSMPS | power_in | Supply input of the SMPS step-down converter; must be connected to the external power supply within the permitted range. |
| 17 | VFBSMPS | power_in | Feedback pin of the SMPS step-down converter, used by the converter to regulate its output. |
| 18 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 19 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 20 | PF6 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC3_INN4 and ADC3_INP8 analog inputs; alternate functions include TIM16_CH1, SPI5_NSS, UART7_RX and QUADSPI_BK1_IO3. |
| 21 | PF7 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC3_INP3 analog input; alternate functions include TIM17_CH1, SPI5_SCK, UART7_TX and QUADSPI_BK1_IO2. |
| 22 | PF8 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC3_INN3 and ADC3_INP7 analog inputs; alternate functions include TIM16_CH1N, SPI5_MISO, TIM13_CH1 and QUADSPI_BK1_IO0. |
| 23 | PF9 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC3_INP2 analog input; alternate functions include TIM17_CH1N, SPI5_MOSI, TIM14_CH1 and QUADSPI_BK1_IO1. |
| 24 | PF10 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC3_INN2 and ADC3_INP6 analog inputs; alternate functions include TIM16_BKIN, SAI1_D3, QUADSPI_CLK, DCMI_D11 and LCD_DE. |
| 25 | PH0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT) that also serves as the OSC_IN oscillator input function. |
| 26 | PH1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT) that also serves as the OSC_OUT oscillator output function. |
| 27 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (RST structure). |
| 28 | PC0 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC123_INP10 analog input; alternate functions include DFSDM1_CKIN0, SAI2_FS_B, OTG_HS_ULPI_STP and FMC_SDNWE. |
| 29 | PC1 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC123_INN10 and ADC123_INP11 analog inputs and RTC_TAMP3/WKUP5 additional functions; alternate functions include SAI1_D1, SPI2_MOSI/I2S2_SDO and ETH_MDC. |
| 30 | PC2_C | passive | Analog pad of PC2 (TT_a structure, 3.3 V-tolerant) that is a separate pad from PC2 unless the analog switch is closed, with ADC3_INN1 and ADC3_INP0 analog inputs. |
| 31 | PC3_C | passive | Analog pad of PC3 (TT_a structure, 3.3 V-tolerant) that is a separate pad from PC3 unless the analog switch is closed, with ADC3_INP1 analog input. |
| 32 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 33 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 34 | VSSA | power_in | Analog ground pin for the analog domain (ADC, DAC, comparators, OPAMP and reference). |
| 35 | VREF+ | power_in | Positive reference voltage pin for the ADC and DAC analog domain. |
| 36 | VDDA | power_in | Analog supply pin for the ADC, DAC, OPAMP and comparators, referenced to VSSA. |
| 37 | PA0 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC1_INP16 analog input and WKUP0 wakeup function; alternate functions include TIM2_CH1/TIM2_ETR, USART2_CTS, UART4_TX and ETH_MII_CRS. |
| 38 | PA1 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC1_INN16 and ADC1_INP17 analog inputs; alternate functions include TIM2_CH2, USART2_RTS/USART2_DE, UART4_RX and LCD_R2. |
| 39 | PA2 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC12_INP14 analog input and WKUP1 wakeup function; alternate functions include TIM2_CH3, USART2_TX, ETH_MDIO and LCD_R1. |
| 40 | PA3 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); ADC12_INP15 analog input; alternate functions include TIM2_CH4, USART2_RX, OTG_HS_ULPI_D0 and ETH_MII_COL. |
| 41 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 42 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 43 | PA4 | bidirectional | 3.3 V-tolerant I/O with analog option (TT_a); ADC12_INP18 analog input and DAC1_OUT1 output; alternate functions include D1PWREN, SPI1_NSS/I2S1_WS, USART2_CK and DCMI_HSYNC. |
| 44 | PA5 | bidirectional | 3.3 V-tolerant I/O with high-speed and analog options (TT_ha); ADC12_INN18 and ADC12_INP19 analog inputs and DAC1_OUT2 output; alternate functions include D2PWREN, TIM2_CH1/TIM2_ETR, SPI1_SCK/I2S1_CK and OTG_HS_ULPI_CK. |
| 45 | PA6 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC12_INP3 analog input; alternate functions include TIM1_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI, TIM13_CH1 and DCMI_PIXCLK. |
| 46 | PA7 | bidirectional | 3.3 V-tolerant I/O with analog option (TT_a); ADC12_INN3, ADC12_INP7 and OPAMP1_VINM analog functions; alternate functions include TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SDO and FMC_SDNWE. |
| 47 | PC4 | bidirectional | 3.3 V-tolerant I/O with analog option (TT_a); ADC12_INP4, OPAMP1_VOUT and COMP1_INM analog functions; alternate functions include I2S1_MCK, SPDIFRX1_IN3, ETH_MII_RXD0 and FMC_SDNE0. |
| 48 | PC5 | bidirectional | 3.3 V-tolerant I/O with analog option (TT_a); ADC12_INN4, ADC12_INP8 and OPAMP1_VINM analog functions; alternate functions include SAI1_D3, SPDIFRX1_IN4, ETH_MII_RXD1, FMC_SDCKE0 and COMP1_OUT. |
| 49 | PB0 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC12_INN5, ADC12_INP9, OPAMP1_VINP and COMP1_INP analog functions; alternate functions include TIM1_CH2N, TIM3_CH3, UART4_CTS and OTG_HS_ULPI_D1. |
| 50 | PB1 | bidirectional | 3.3 V-tolerant USB-option I/O (TT_u, supplied by VDD33USB); ADC12_INP5 and COMP1_INM analog functions; alternate functions include TIM1_CH3N, TIM3_CH4, DFSDM1_DATIN1 and OTG_HS_ULPI_D2. |
| 51 | PB2 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); COMP1_INP analog function; alternate functions include RTC_OUT, SAI1_D1, DFSDM1_CKIN1, SPI3_MOSI/I2S3_SDO and QUADSPI_CLK. |
| 52 | PF11 | bidirectional | 5 V-tolerant I/O with analog option (FT_a); ADC1_INP2 analog input; alternate functions include SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS and DCMI_D12. |
| 53 | PF14 | bidirectional | 5 V-tolerant I/O with I2C FM+, high-speed and analog options (FT_fha); ADC2_INN2 and ADC2_INP6 analog inputs; alternate functions include DFSDM1_CKIN6, I2C4_SCL and FMC_A8. |
| 54 | PF15 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include I2C4_SDA and FMC_A9. |
| 55 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 56 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 57 | PE7 | bidirectional | 3.3 V-tolerant I/O with high-speed and analog options (TT_ha); OPAMP2_VOUT and COMP2_INM analog functions; alternate functions include TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0 and FMC_D4. |
| 58 | PE8 | bidirectional | 3.3 V-tolerant I/O with high-speed and analog options (TT_ha); OPAMP2_VINM and COMP2_OUT analog functions; alternate functions include TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1 and FMC_D5. |
| 59 | PE9 | bidirectional | 3.3 V-tolerant I/O with high-speed and analog options (TT_ha); OPAMP2_VINP and COMP2_INP analog functions; alternate functions include TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, QUADSPI_BK2_IO2 and FMC_D6. |
| 60 | PE10 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); COMP2_INM analog function; alternate functions include TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3 and FMC_D7. |
| 61 | PE11 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); COMP2_INP analog function; alternate functions include TIM1_CH2, SPI4_NSS, SAI2_SD_B, FMC_D8 and LCD_G3. |
| 62 | PE12 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9, COMP1_OUT and LCD_B4. |
| 63 | PE13 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10, COMP2_OUT and LCD_DE. |
| 64 | PE14 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11 and LCD_CLK. |
| 65 | PE15 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM1_BKIN, FMC_D12, TIM1_BKIN_COMP12 and LCD_R7. |
| 66 | PB10 | bidirectional | 5 V-tolerant I/O with I2C FM+ option (FT_f); alternate functions include TIM2_CH3, HRTIM_SCOUT, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, QUADSPI_BK1_NCS and OTG_HS_ULPI_D3. |
| 67 | PB11 | bidirectional | 5 V-tolerant I/O with I2C FM+ option (FT_f); alternate functions include TIM2_CH4, HRTIM_SCIN, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4 and ETH_MII_TX_EN. |
| 68 | VCAP | power_out | Main regulator stabilization pin; an external capacitor CEXT of 2.2 µF with ESR below 100 mΩ must be connected to it. |
| 69 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 70 | VDDLDO | power_in | Supply input of the embedded LDO regulator that supplies the digital circuitry. |
| 71 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 72 | PB12 | bidirectional | 5 V-tolerant USB-option I/O (FT_u, supplied by VDD33USB); alternate functions include TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5 and OTG_HS_ID. |
| 73 | PB13 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); additional OTG_HS_VBUS function; alternate functions include TIM1_CH1N, LPTIM2_OUT, USART3_CTS, FDCAN2_TX, OTG_HS_ULPI_D6 and UART5_TX. |
| 74 | PB14 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); alternate functions include TIM1_CH2N, TIM12_CH1, USART1_TX, SPI2_MISO/I2S2_SDI, SDMMC2_D0 and OTG_HS_DM. |
| 75 | PB15 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); alternate functions include RTC_REFIN, TIM1_CH3N, TIM12_CH2, USART1_RX, SPI2_MOSI/I2S2_SDO, SDMMC2_D1 and OTG_HS_DP. |
| 76 | PD8 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX1_IN2 and FMC_D13. |
| 77 | PD9 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_DATIN3, SAI3_SD_B, USART3_RX, FDCAN2_RXFD_MODE and FMC_D14. |
| 78 | PD10 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_CKOUT, SAI3_FS_B, USART3_CK, FDCAN2_TXFD_MODE, FMC_D15 and LCD_B3. |
| 79 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 80 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 81 | PD11 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include LPTIM2_IN2, I2C4_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A and FMC_A16. |
| 82 | PD12 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include LPTIM1_IN1, TIM4_CH1, I2C4_SCL, USART3_RTS, QUADSPI_BK1_IO1 and FMC_A17. |
| 83 | PD13 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include LPTIM1_OUT, TIM4_CH2, I2C4_SDA, QUADSPI_BK1_IO3 and FMC_A18. |
| 84 | PD14 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM4_CH3, SAI3_MCLK_B, UART8_CTS and FMC_D0. |
| 85 | PD15 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM4_CH4, SAI3_MCLK_A, UART8_RTS/UART8_DE and FMC_D1. |
| 86 | PG6 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM17_BKIN, HRTIM_CHE1, QUADSPI_BK1_NCS, FMC_NE3, DCMI_D12 and LCD_R7. |
| 87 | PG7 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_CHE2, SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13 and LCD_CLK. |
| 88 | PG8 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TIM8_ETR, SPI6_NSS, USART6_RTS/USART6_DE, SPDIFRX1_IN3, ETH_PPS_OUT, FMC_SDCLK and LCD_G7. |
| 89 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 90 | VDD50USB | power_in | 5 V supply input of the USB power block, whose embedded 3.3 V regulator supplies the internal USB PHYs. |
| 91 | VDD33USB | power_in | USB supply pin specified at 3.0 to 3.6 V, supplying the USB option I/Os and internal USB PHYs. |
| 92 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 93 | PC6 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_CHA1, TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, FMC_NWAIT and DCMI_D0; additional SWPMI_IO function. |
| 94 | PC7 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRGIO, HRTIM_CHA2, TIM3_CH2, I2S3_MCK, USART6_RX, FMC_NE1, SWPMI_TX and DCMI_D1. |
| 95 | PC8 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRACED1, HRTIM_CHB1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE, FMC_NE2/FMC_NCE and SWPMI_RX. |
| 96 | PC9 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, UART5_CTS, QUADSPI_BK1_IO0 and SWPMI_SUSPEND. |
| 97 | PA8 | bidirectional | 5 V-tolerant I/O with I2C FM+, high-speed and analog options (FT_fha); alternate functions include MCO1, TIM1_CH1, HRTIM_CHB2, I2C3_SCL, USART1_CK, OTG_FS_SOF and UART7_RX. |
| 98 | PA9 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); additional OTG_FS_VBUS function; alternate functions include TIM1_CH2, HRTIM_CHC1, LPUART1_TX, I2C3_SMBA, USART1_TX, FDCAN1_RXFD_MODE and DCMI_D0. |
| 99 | PA10 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); alternate functions include TIM1_CH3, HRTIM_CHC2, LPUART1_RX, USART1_RX, FDCAN1_TXFD_MODE, OTG_FS_ID, MDIOS_MDIO and DCMI_D1. |
| 100 | PA11 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); alternate functions include TIM1_CH4, HRTIM_CHD1, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS, FDCAN1_RX and OTG_FS_DM. |
| 101 | PA12 | bidirectional | 5 V-tolerant USB-option I/O (FT_u); alternate functions include TIM1_ETR, HRTIM_CHD2, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, FDCAN1_TX and OTG_FS_DP. |
| 102 | PA13 (JTMS/SWDIO) | bidirectional | 5 V-tolerant I/O (FT) carrying the JTMS-SWDIO debug function, with EVENTOUT as alternate function. |
| 103 | VCAP | power_out | Main regulator stabilization pin; an external capacitor CEXT of 2.2 µF with ESR below 100 mΩ must be connected to it. |
| 104 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 105 | VDDLDO | power_in | Supply input of the embedded LDO regulator that supplies the digital circuitry. |
| 106 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 107 | PA14 (JTCK/SWCLK) | bidirectional | 5 V-tolerant I/O (FT) carrying the JTCK-SWCLK debug function, with EVENTOUT as alternate function. |
| 108 | PA15(JTDI) | bidirectional | 5 V-tolerant I/O (FT) carrying the JTDI debug function; alternate functions include TIM2_CH1/TIM2_ETR, HRTIM_FLT1, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS and UART4_RTS/UART4_DE. |
| 109 | PC10 | bidirectional | 5 V-tolerant I/O with high-speed and analog options (FT_ha); alternate functions include HRTIM_EEV1, DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2 and DCMI_D8. |
| 110 | PC11 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_FLT2, DFSDM1_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3 and DCMI_D4. |
| 111 | PC12 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRACED3, HRTIM_EEV2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK and DCMI_D9. |
| 112 | PD0 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_CKIN6, SAI3_SCK_A, UART4_RX, FDCAN1_RX and FMC_D2. |
| 113 | PD1 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_DATIN6, SAI3_SD_A, UART4_TX, FDCAN1_TX and FMC_D3. |
| 114 | PD2 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD and DCMI_D11. |
| 115 | PD3 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5 and LCD_G7. |
| 116 | PD4 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_FLT3, SAI3_FS_A, USART2_RTS/USART2_DE, FDCAN1_RXFD_MODE and FMC_NOE. |
| 117 | PD5 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_EEV3, USART2_TX, FDCAN1_TXFD_MODE and FMC_NWE. |
| 118 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 119 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 120 | PD6 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include SAI1_D1, DFSDM1_CKIN4, SPI3_MOSI/I2S3_SDO, USART2_RX, SDMMC2_CK, FMC_NWAIT, DCMI_D10 and LCD_B2. |
| 121 | PD7 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include DFSDM1_DATIN4, SPI1_MOSI/I2S1_SDO, DFSDM1_CKIN1, USART2_CK, SPDIFRX1_IN1, SDMMC2_CMD and FMC_NE1. |
| 122 | PG9 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX1_IN4, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE and DCMI_VSYNC. |
| 123 | PG10 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include HRTIM_FLT5, SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, FMC_NE3, DCMI_D2 and LCD_B2. |
| 124 | PG11 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include LPTIM1_IN2, HRTIM_EEV4, SPI1_SCK/I2S1_CK, SPDIFRX1_IN1, SDMMC2_D2, ETH_MII_TX_EN and DCMI_D3. |
| 125 | PG12 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include LPTIM1_IN1, HRTIM_EEV5, SPI6_MISO, USART6_RTS/USART6_DE, SPDIFRX1_IN2, ETH_MII_TXD1, FMC_NE4 and LCD_B1. |
| 126 | PG13 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRACED0, LPTIM1_OUT, HRTIM_EEV10, SPI6_SCK, USART6_CTS, ETH_MII_TXD0, FMC_A24 and LCD_R0. |
| 127 | PG14 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1, FMC_A25 and LCD_B0. |
| 128 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 129 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
| 130 | PB3 (JTDO/TRACESWO) | bidirectional | 5 V-tolerant I/O (FT) carrying the JTDO/TRACESWO debug function; alternate functions include TIM2_CH2, HRTIM_FLT4, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SDMMC2_D2 and UART7_RX. |
| 131 | PB4 (NJTRST) | bidirectional | 5 V-tolerant I/O (FT) carrying the NJTRST debug function; alternate functions include TIM16_BKIN, TIM3_CH1, HRTIM_EEV6, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SDMMC2_D3 and UART7_TX. |
| 132 | PB5 | bidirectional | 5 V-tolerant I/O (FT); alternate functions include TIM17_BKIN, TIM3_CH2, HRTIM_EEV7, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, FDCAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10 and UART5_RX. |
| 133 | PB6 | bidirectional | 5 V-tolerant I/O with I2C FM+ option (FT_f); alternate functions include TIM16_CH1N, TIM4_CH1, HRTIM_EEV8, I2C1_SCL, CEC, I2C4_SCL, USART1_TX, FDCAN2_TX, QUADSPI_BK1_NCS and FMC_SDNE1. |
| 134 | PB7 | bidirectional | 5 V-tolerant I/O with I2C FM+ and analog options (FT_fa); additional PVD_IN function; alternate functions include TIM17_CH1N, TIM4_CH2, HRTIM_EEV9, I2C1_SDA, I2C4_SDA, USART1_RX, FDCAN2_TXFD_MODE and FMC_NL. |
| 135 | BOOT0 | input | Dedicated BOOT0 input pin, with a maximum input voltage of 9.0 V (VPP). |
| 136 | PB8 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX and DCMI_D6. |
| 137 | PB9 | bidirectional | 5 V-tolerant I/O with I2C FM+ and high-speed options (FT_fh); alternate functions include TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, UART4_TX, FDCAN1_TX and DCMI_D7. |
| 138 | PE0 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include LPTIM1_ETR, TIM4_ETR, HRTIM_SCIN, LPTIM2_ETR, UART8_RX, SAI2_MCLK_A, FMC_NBL0 and DCMI_D2. |
| 139 | PE1 | bidirectional | 5 V-tolerant I/O with high-speed option (FT_h); alternate functions include LPTIM1_IN2, HRTIM_SCOUT, UART8_TX, FDCAN1_TXFD_MODE, FMC_NBL1 and DCMI_D3. |
| 140 | VCAP | power_out | Main regulator stabilization pin; an external capacitor CEXT of 2.2 µF with ESR below 100 mΩ must be connected to it. |
| 141 | VSS | power_in | Ground pin; all VSS pins must be at the same potential, with ground variations limited to 50 mV. |
| 142 | PDR_ON | input | 5 V-tolerant (FT) input pin for the power-down reset control, PDR_ON. |
| 143 | VDDLDO | power_in | Supply input of the embedded LDO regulator that supplies the digital circuitry. |
| 144 | VDD | power_in | Digital and I/O supply pin of the 1.62 to 3.6 V application supply; VDD pin-to-pin variations within the domain are limited to 50 mV. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-144(20x20) |
| Category | Global Sourcing Parts |
| Pins | 144 |
CAD (KiCad official)
- Symbol:
STM32H755ZIT6 - Footprint:
Package_QFP:LQFP-144_20x20mm_P0.5mm - 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files:
stm32h755zit6-etched.step/stm32h755zit6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32h755zit6.step/stm32h755zit6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (252 pp, sha256
95fcf29e96c85204, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).