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Contents

README

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TPS62140ARGTT

Texas Instruments · DC-DC Converters · TQFN-16-EP(3x3)

TPS62140ARGTT from Texas Instruments, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor.
2 SW output Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor.
3 SW output Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor.
4 PG output Open-drain power-good output: high means VOUT is ready, low means VOUT is below nominal regulation; requires a pullup resistor.
5 FB input Voltage feedback input of the adjustable version; connect a resistive voltage divider to this pin, and connect it to AGND on fixed-output versions for improved thermal performance.
6 AGND power_in Analog ground; must be connected directly to the exposed thermal pad and the common ground plane.
7 FSW input Switching frequency select: low gives about 2.5 MHz and high gives about 1.25 MHz (connect to VOUT or PG for high); an internal pulldown keeps it low if floating.
8 DEF input Output voltage scaling: low selects nominal output and high selects nominal plus 5%; an internal pulldown keeps it low if floating.
9 SS/TR input Soft-start and tracking input; an external capacitor on this pin sets the internal voltage reference rise time and can be used for tracking and sequencing.
10 AVIN power_in Supply voltage for the control circuitry; connect to the same source as PVIN.
11 PVIN power_in Supply voltage for the power stage; connect to the same source as AVIN.
12 PVIN power_in Supply voltage for the power stage; connect to the same source as AVIN.
13 EN input Enable input: high enables the device and low disables it; an internal pulldown keeps it low if floating.
14 VOS input Output voltage sense pin and connection for the control loop circuitry.
15 PGND power_in Power ground; must be connected directly to the exposed thermal pad and the common ground plane.
16 PGND power_in Power ground; must be connected directly to the exposed thermal pad and the common ground plane.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS62140ARGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps62140argtt-etched.step / tps62140argtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62140argtt.step / tps62140argtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 4bee4a4bd05d3236, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF