component
DAC53001RTER
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC53001RTER
Texas Instruments · Digital To Analog Converters (DAC) · WQFN-16(3x3)
DAC53001RTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB0 | input | Voltage feedback pin for channel 0; connect to OUT0 in voltage-output mode for closed-loop amplifier output, and leave unconnected in current-output mode to minimize leakage current. |
| 2 | OUT0 | output | Analog output voltage from DAC channel 0. |
| 3 | NC | unconnected | No connection; leave this pin unconnected. |
| 4 | NC | unconnected | No connection; leave this pin unconnected. |
| 5 | GPIO/SDO | bidirectional | General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS; for STATUS and SDO use an external pullup to the IO voltage, if unused connect to VDD or AGND through a resistor, and the pin can ramp up before VDD. |
| 6 | SCL/SYNC | input | I2C serial interface clock or SPI chip select input; must be connected to the IO voltage with an external pullup resistor and can ramp up before VDD. |
| 7 | A0/SDI | input | I2C address configuration pin (connect to VDD, AGND, SDA, or SCL) or SPI serial data input (no pullup or pulldown needed); can ramp up before VDD. |
| 8 | SDA/SCLK | bidirectional | Bidirectional I2C serial data bus or SPI clock input; requires an external pullup to the IO voltage in I2C mode and can ramp up before VDD. |
| 9 | NC | unconnected | No connection; leave this pin unconnected. |
| 10 | NC | unconnected | No connection; leave this pin unconnected. |
| 11 | OUT1/NC | unconnected | On DAC53001 (single-channel) this is a no-connect pin; leave it unconnected (it is the channel 1 analog output on DAC53002/DAC63002). |
| 12 | FB1/NC | unconnected | On DAC53001 (single-channel) this is a no-connect pin; leave it unconnected (it is the channel 1 feedback pin on DAC53002/DAC63002). |
| 13 | CAP | passive | External bypass capacitor connection for the internal LDO; connect approximately 1.5 μF between CAP and AGND (CCAP allowed 0.5 to 15 μF). |
| 14 | AGND | power_in | Ground reference point for all circuitry on the device. |
| 15 | VDD | power_in | Supply voltage, 1.7 V to 5.5 V recommended operating range (absolute maximum 6 V). |
| 16 | VREF | power_in | External reference input; connect approximately 0.1 μF to AGND, use a pullup resistor to VDD when the external reference is unused, and it must not ramp up before VDD. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16(3x3) |
| Category | Data Acquisition |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD to AGND | VDD | -0.3 | 6 | V | 4 | ||
| Digital inputs to AGND | -0.3 | V | max VDD + 0.3 V | 4 | |||
| CAP to AGND | -0.3 | 1.65 | V | 4 | |||
| Current into any pin except OUTx | -10 | 10 | mA | 4 | |||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Positive supply voltage | VDD | 1.7 | 5.5 | V | 4 | ||
| External reference | VREF | 1.7 | V | max VDD | 4 | ||
| Digital input high voltage | VIH | 1.62 | V | 1.7 V < VDD ≤ 5.5 V | 4 | ||
| Digital input low voltage | VIL | 0.4 | V | 4 | |||
| External capacitor on CAP pin | CCAP | 0.5 | 15 | μF | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 49 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 50 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 24.1 | °C/W | 4 | |||
| Integral nonlinearity | INL | -1 | 1 | LSB | DAC53002, DAC53001 (10-bit), voltage output | 5 | |
| Differential nonlinearity | DNL | -1 | 1 | LSB | voltage output | 5 | |
| Offset error | -0.75 | 0.3 | 0.75 | %FSR | 1.7 V ≤ VDD < 2.7 V, FBx shorted to OUTx, DAC code 8d for 10-bit | 5 | |
| Offset error | -0.5 | 0.25 | 0.5 | %FSR | 2.7 V ≤ VDD ≤ 5.5 V, FBx shorted to OUTx, DAC code 8d for 10-bit | 5 | |
| Gain error | -0.5 | 0.25 | 0.5 | %FSR | Between end-point codes: 8d to 1016d for 10-bit | 5 | |
| Full-scale error | -1 | 1 | %FSR | 1.7 V ≤ VDD < 2.7 V, DAC at full-scale | 5 | ||
| Full-scale error | -0.5 | 0.5 | %FSR | 2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale | 5 | ||
| DC output impedance | ZO | 400 | 500 | 600 | kΩ | DAC output enabled, internal reference (gain = 1.5x or 2x) or external reference at VDD (gain = 1x) | 5 |
| DC output impedance | ZO | 325 | 400 | 485 | kΩ | DAC output enabled, internal VREF, gain = 3x or 4x | 5 |
| Current flowing into VDD, voltage output | IDD | 35 | 50 | µA/ch | Normal operation, DACs at full scale, digital pins static, external reference at VDD | 6 | |
| Current output INL | INL | -1 | 1 | LSB | DAC codes between 0d and 255d for other ranges | 7 | |
| Current output DNL | DNL | -1 | 1 | LSB | DAC codes between 0d and 255d for other ranges | 7 | |
| Comparator offset error | -5 | 0 | 5 | mV | 1.7 V ≤ VDD ≤ 5.5 V, DAC at midscale, comparator input at Hi-Z, external reference | 8 | |
| Internal reference initial accuracy | 1.1979 | 1.212 | 1.224 | V | TA = 25°C | 9 | |
| Current flowing into VDD, deep-sleep | IDD | 1.5 | 3 | µA | DAC in deep-sleep mode, internal reference powered down, SDO mode disabled | 9 | |
| Reference output temperature coefficient | 50 | ppm/°C | 9 | ||||
| EEPROM endurance | 20000 | Cycles | -40°C ≤ TA ≤ +85°C | 9 | |||
| EEPROM endurance | 1000 | Cycles | TA = 125°C | 9 | |||
| I2C standard mode SCL frequency | fSCLK | 100 | kHz | 10 | |||
| I2C fast mode SCL frequency | fSCLK | 400 | kHz | 10 | |||
| I2C fast mode plus SCL frequency | fSCLK | 1 | MHz | 10 | |||
| Zero-code error temperature coefficient | -10 | 10 | µV/°C | Code 0d into DAC | 5 |
CAD (KiCad official)
- Symbol:
DAC53001RTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac53001rter-etched.step/dac53001rter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac53001rter.step/dac53001rter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (85 pp, sha256
220a6481d4c25cfd, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).