component
TPD2S701QDSKRQ1
Public Made by Adomby adom
Texas Instruments USB Converters, SON-10-EP(2.5x2.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPD2S701QDSKRQ1
Texas Instruments · USB Converters · SON-10-EP(2.5x2.5)
TPD2S701QDSKRQ1 from Texas Instruments, in a SON-10-EP(2.5x2.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VD- | bidirectional | High-voltage D- USB data line that connects to the USB connector, with IEC61000-4-2 ESD protection; the VD+/VD- voltage range is -0.3 V to 7.7 V. |
| 2 | VD+ | bidirectional | High-voltage D+ USB data line that connects to the USB connector, with IEC61000-4-2 ESD protection; the VD+/VD- voltage range is -0.3 V to 7.7 V. |
| 3 | GND | power_in | Ground pin for the internal circuits and the IEC ESD clamps. |
| 4 | FLT | output | Open-drain fault pin that is asserted low on overvoltage or thermal shutdown and is pulled high externally; the absolute maximum voltage is 7.7 V. |
| 5 | EN | input | Active-low enable input: driving EN low enables the data switches and driving it high disables them; the absolute maximum voltage is 7.7 V. |
| 6 | MODE | input | Selects the device mode (Mode 0 when the resistance to GND is at most 2.6 kΩ, Mode 1 when Rtop |
| 7 | VPWR | power_in | 5-V DC supply input for the internal circuits, to be connected to the internal power rail on the PCB; the absolute maximum rating is -0.3 V to 7.7 V. |
| 8 | VREF | power_in | Pin that sets the OVP threshold, with an absolute maximum range of -0.3 V to 6 V; it is driven by an external regulator in Mode 0 or by the internal adjustable regulator in Mode 1 (0.6 V to 3.8 V). |
| 9 | D+ | bidirectional | Protected low-voltage D+ USB data line that connects to the transceiver, with an internal range of up to VREF + 0.3 V. |
| 10 | D- | bidirectional | Protected low-voltage D- USB data line that connects to the transceiver, with an internal range of up to VREF + 0.3 V. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-10-EP(2.5x2.5) |
| Category | Interface |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VPWR 5-V DC supply voltage for internal circuitry | VPWR | -0.3 | 7.7 | V | 4 | ||
| Pin to set OVP threshold | VREF | -0.3 | 6 | V | 4 | ||
| Voltage range from connector-side USB data lines | VD+, VD- | -0.3 | 7.7 | V | 4 | ||
| Voltage range for internal USB data lines | D+, D- | -0.3 | V | Printed maximum is VREF + 0.3 V | 4 | ||
| Voltage on MODE pin | VMODE | -0.3 | 7.7 | V | 4 | ||
| Voltage on FLT pin | VFLT | -0.3 | 7.7 | V | 4 | ||
| Voltage on enable pin | VEN | -0.3 | 7.7 | V | 4 | ||
| Operating free air temperature | TA | -40 | 125 | °C | 4 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| 5-V DC supply voltage for internal circuitry | VPWR | 4.5 | 7 | V | 5 | ||
| Voltage range for VREF pin (for setting OVP threshold) | VREF | 3 | 3.6 | V | Mode 0 | 5 | |
| Voltage range for VREF pin (for setting OVP threshold) | VREF | 0.63 | 3.8 | V | Mode 1 | 5 | |
| Voltage range from connector-side USB data lines | VD+, VD- | 0 | 3.6 | V | 5 | ||
| Voltage range for internal USB data lines | D+, D- | 0 | 3.6 | V | 5 | ||
| Voltage range for enable | VEN | 0 | 7 | V | 5 | ||
| Voltage range for FLT | VFLT | 0 | 7 | V | 5 | ||
| Current into open drain FLT pin FET | IFLT | 0 | 3 | mA | 5 | ||
| VPWR capacitance | CVPWR | 1 | 10 | µF | External capacitor on VPWR pin | 5 | |
| VREF capacitance | CVREF | 0.3 | 1 | 3 | µF | External capacitor on VREF pin | 5 |
| Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors | CMODE | 20 | pF | 5 | |||
| Resistance to GND to set to mode 0 | RMODE_0 | 2 | 2.6 | kΩ | 5 | ||
| Resistance to GND to set to mode 1 | RMODE_1 | 14 | 20 | kΩ | Calculate parallel combination of RTOP and RBOT | 5 | |
| Mode 1 VREF feedback regulator voltage | VMODE_CMP | 0.47 | 0.5 | 0.53 | V | Standard mode 1 set-up. EN = 0 V. Once VREF = 3.3 V, measure voltage on mode pin | 6 |
| Mode pin mode 1 leakage current | IMODE_LEAK | 50 | 200 | nA | Standard mode 1, RTOP and RBOT removed. Force 0.53 V on MODE pin, measure current into pin | 6 | |
| VREF accuracy | VREF_ACCURACY | -8 | 8 | % | Informative; accuracy with RTOP and RBOT as ±1% resistors | 6 | |
| Mode 1 VREF set to 3.3 V | VREF_3.3V | 3.04 | 3.31 | 3.58 | V | Standard mode 1 set-up. RTOP = 140 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. EN = 0. Measure VREF once it settles | 6 |
| Mode 1 VREF set to 0.66 V | VREF_0.66V | 0.6 | 0.66 | 0.72 | V | Standard mode 1 set-up. RTOP = 47.5 kΩ ± 1%, RBOT = 150 kΩ ± 1%. EN = 0. Measure VREF once it settles | 6 |
| Mode 1 VREF set to 3.8 V | VREF_3.8V | 3.5 | 3.81 | 4.12 | V | Standard mode 1 set-up. RTOP = 165 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. EN = 0. Measure VREF once it settles | 6 |
| High-level input voltage EN | VIH | 1.2 | V | Mode 0. VPWR = 5 V; VREF = 3.3 V; VD+ = 3.3 V; sweep EN from 0 V to 1.4 V | 6 | ||
| Low-level input voltage EN | 0.8 | V | Mode 0. VPWR = 5 V; VREF = 3.3 V; VD+ = 3.3 V; sweep EN from 3.3 V to 0.5 V | 6 | |||
| Input leakage current EN | IIL | 1 | µA | Mode 0. VPWR = 5 V; VREF = 3.3 V; VI(EN) = 3.3 V; measure current into EN pin | 6 | ||
| Low-level output voltage FLT | VOL | 0.4 | V | Mode 0. Drive into OVP to assert FLT; source IOL = 1 mA into FLT pin | 6 | ||
| The rising over temperature protection shutdown threshold | TSD_RISING | 140 | 150 | 165 | °C | VPWR = 5 V, ENZ = 0 V, TA stepped up until FLTZ is asserted | 6 |
| The falling over temperature protection shutdown threshold | TSD_FALLING | 125 | 138 | 150 | °C | VPWR = 5 V, ENZ = 0 V, TA stepped down from TSD_RISING until FLTZ is cleared | 6 |
| The over temperature protection shutdown threshold hysteresis | TSD_HYST | 10 | 12 | 15 | °C | TSD_RISING, TSD_FALLING | 6 |
| Input overvoltage protection threshold, VREF > 3.6 V | VOVP_RISING | 4.3 | 4.5 | 4.7 | V | Mode 1. VPWR = 5 V; EN = 0 V; RTOP = 165 kΩ, RBOT = 24.9 kΩ; D± into 40-Ω load; VD± increased from 4.1 V to 4.9 V | 6 |
| Input overvoltage protection threshold VD± | VOVP_RISING | 1.19 | 1.25 | 1.31 | ×VREF | Mode 1. VPWR = 5 V; EN = 0 V; RTOP = 140 kΩ, RBOT = 24.9 kΩ (also 39 kΩ / 150 kΩ) | 6 |
| Leakage current on VD± during normal operation | IVD_LEAK_0V | -0.1 | 0.1 | µA | Standard mode 0 or mode 1. VD± = 0 V; D± floating | 6 | |
| Leakage current on VD± during normal operation | IVD_LEAK_3.6V | 2.5 | 4 | µA | Standard mode 0 or mode 1. VD± = 3.6 V; D± floating | 7 | |
| Input overvoltage threshold for VREF = 3.3 V | VOVP_3.3V | 3.61 | 4.14 | 4.67 | V | Standard mode 1. RTOP = 140 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. D± into 40-Ω load | 7 |
| Input overvoltage threshold for VREF = 0.66 V | VOVP_0.66V | 0.72 | 0.83 | 0.94 | V | Standard mode 1. RTOP = 47.5 kΩ ± 1%, RBOT = 150 kΩ ± 1%. D± into 40-Ω load | 7 |
| On resistance | RON | 4 | 6.5 | Ω | Mode 0 or 1. VPWR = 5 V; VREF = 3.3 V; EN = 0 V; voltage between 0 and 0.4 V | 7 | |
| On resistance flatness | RON(Flat) | 1 | Ω | Mode 0 or 1. VPWR = 5 V; VREF = 3.3 V; EN = 0 V; difference of resistance at 0.4 V and 0 V bias | 7 | ||
| VPWR rising UVLO threshold | VUVLO_RISING_VPWR | 3.7 | 3.95 | 4.2 | V | Standard mode 0. EN = 0 V; D+ loaded to 45 Ω; VD+ = 3.3 V; step VPWR up until 90% of VD+ appears on D+ | 7 |
| VPWR UVLO hysteresis | VUVLO_HYST_VPWR | 250 | 300 | 400 | mV | Standard mode 0. EN = 0 V; D+ loaded to 45 Ω; VD+ = 3.3 V | 7 |
| VREF rising UVLO threshold in mode 0 | VUVLO_RISING_VREF | 2.6 | 2.7 | 2.9 | V | Standard mode 0. EN = 0 V; D+ loaded to 45 Ω; VD+ = 3.3 V; step VREF up until 90% of VD+ appears on D+ | 7 |
| VREF UVLO hysteresis | VUVLO_HYST_VREF | 75 | 125 | 200 | mV | Standard mode 0. EN = 0 V; D+ loaded to 45 Ω; VD+ = 3.3 V | 7 |
| VPWR disabled current consumption | IVPWR_DISABLE_MODE0 | 110 | µA | Standard mode 0. EN = 5 V. Measure current into VPWR | 7 | ||
| VREF disabled current consumption mode 0 | IVREF_DISABLE_MODE0 | 10 | µA | Standard mode 0. EN = 5 V. Measure current into VREF | 7 | ||
| VPWR operating current consumption | IVPWR_MODE0 | 250 | µA | Standard mode 0. EN = 0 V. Measure current into VPWR | 7 | ||
| VPWR operating current consumption | IVPWR_MODE1 | 350 | µA | Standard mode 1. EN = 0 V. Measure current into VPWR | 7 | ||
| VREF operating current consumption mode 0 | IVREF | 12 | 20 | µA | Standard mode 0. EN = 0 V. Measure current into VREF | 7 | |
| Mode 0 leakage into D+ or D- supply (off state) | ID_OFF_LEAK_STB | -1 | 1 | µA | Mode 0. Measured flowing into D+ or D- supply, VPWR = 0 V, VD± = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V | 8 | |
| Mode 0 leakage into D+ or D- supply (on state) | ID_ON_LEAK_STB | -1 | 1 | µA | Mode 0. Measured flowing into D+ or D- supply, VPWR = 5 V, VD± = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V | 8 | |
| Mode 0 leakage out of VD+ or VD- supply (on state) | IVD_ON_LEAK_STB | 120 | µA | Mode 0. Measured flowing out of VD+ or VD- supply, VPWR = 5 V, VD± = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V | 8 | ||
| Junction-to-ambient thermal resistance | θJA | 61.5 | °C/W | DSK (WSON), 10 pins | 5 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 51.3 | °C/W | DSK (WSON), 10 pins | 5 | ||
| Junction-to-board thermal resistance | θJB | 34 | °C/W | DSK (WSON), 10 pins | 5 | ||
| Junction-to-case (bottom) thermal resistance | θJCbot | 7.7 | °C/W | DSK (WSON), 10 pins | 5 |
CAD (KiCad official)
- Symbol:
TPD2S701QDSKRQ1 - Footprint:
Package_SON:WSON-10-1EP_2.5x2.5mm_P0.5mm_EP1.2x2mm - 3D model: SON-10-EP(2.5x2.5) (KiCad packages3D, STEP)
- 3D model files:
tpd2s701qdskrq1-etched.step/tpd2s701qdskrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpd2s701qdskrq1.step/tpd2s701qdskrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
355ef577b1bd4b7e, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).