TLV4110IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No internal connection.
2	IN−	input	Inverting input of the operational amplifier; common-mode input range is 0 V to VDD−1.5 V.
3	IN+	input	Non-inverting input of the operational amplifier; common-mode input range is 0 V to VDD−1.5 V.
4	GND	power_in	Ground (negative supply); all voltages except differential voltages are referenced to it.
5	NC	unconnected	No internal connection.
6	OUT	output	Rail-to-rail amplifier output able to deliver more than 300 mA at 5 V, with absolute maximum output current of 800 mA.
7	VDD	power_in	Positive supply, recommended 2.5 V to 6 V and 7 V absolute maximum.
8	SHDN	input	Shutdown control input referenced to GND, with turn-on level 2.1 V at VDD = 3 V and 3.8 V at VDD = 5 V, and turn-off level 0.9 V at 3 V and 1.65 V at 5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	2.5		6	V		3
Common-mode input voltage range	VICR	0			V	max = VDD-1.5	3
Operating free-air temperature, I-suffix	TA	-40		125	°C	I-suffix	3
Supply voltage absolute maximum	VDD			7	V	wrt GND	3
Output current	IO			800	mA	see Note 2	3
Continuous RMS output current	IO			350	mA	TJ ≤ 105°C	3
Continuous RMS output current	IO			110	mA	TJ ≤ 150°C	3
Peak output current	IO			500	mA	TJ ≤ 105°C	3
Peak output current	IO			155	mA	TJ ≤ 150°C	3
Maximum junction temperature	TJ			150	°C		3
Storage temperature	Tstg	-65		150	°C		3
Lead temperature				260	°C	1,6 mm from case for 10 seconds	3
Junction-to-ambient thermal resistance D (8)	θJA		176		°C/W	D (8) package	3
Junction-to-case thermal resistance D (8)	θJC		38.3		°C/W	D (8) package	3
Input offset voltage	VIO		175	3500	µV	VIC = VDD/2, VO = VDD/2, RL = 100 Ω, RS = 50 Ω, 25°C	4
Input offset voltage	VIO			4000	µV	Full range	4
Offset voltage drift	αVIO		3		µV/°C	RL = 100 Ω, RS = 50 Ω, 25°C	4
Common-mode rejection ratio	CMRR	63			dB	VDD = 3 V, VIC = 0 to 2 V, RS = 50 Ω, 25°C	4
Common-mode rejection ratio	CMRR	68			dB	VDD = 5 V, VIC = 0 to 4 V, RS = 50 Ω, 25°C	4
Large-signal differential voltage amplification	AVD	78	84		dB	VDD = 3 V, RL = 100 Ω, VO(PP) = 0 to 1 V, 25°C	4
Large-signal differential voltage amplification	AVD	67			dB	VDD = 3 V, RL = 100 Ω, Full range	4
Large-signal differential voltage amplification	AVD	85	100		dB	VDD = 3 V, RL = 10 kΩ, VO(PP) = 0 to 1 V, 25°C	4
Large-signal differential voltage amplification	AVD	75			dB	VDD = 3 V, RL = 10 kΩ, Full range	4
Large-signal differential voltage amplification	AVD	88	94		dB	VDD = 5 V, RL = 100 Ω, VO(PP) = 0 to 3 V, 25°C	4
Large-signal differential voltage amplification	AVD	90	110		dB	VDD = 5 V, RL = 10 kΩ, VO(PP) = 0 to 3 V, 25°C	4
Large-signal differential voltage amplification	AVD	85			dB	VDD = 5 V, RL = 10 kΩ, Full range	4
Input offset current	IIO		0.3		pA	VIC = VDD/2, 25°C	4
Input offset current	IIO			250	pA	VIC = VDD/2, TLV411xI, Full range	4
Input bias current	IIB		0.3		pA	VO = VDD/2, RS = 50 Ω, 25°C	4
Input bias current	IIB			500	pA	VO = VDD/2, RS = 50 Ω, TLV411xI, Full range	4
Differential input resistance	ri(d)		1000		GΩ	25°C	4
Common-mode input capacitance	CIC		5		pF	f = 100 Hz, 25°C	4
High-level output voltage	VOH	2.7	2.97		V	VDD = 3 V, IOH = -10 mA, VIC = VDD/2, 25°C	5
High-level output voltage	VOH	2.6	2.73		V	VDD = 3 V, IOH = -100 mA, VIC = VDD/2, 25°C	5
High-level output voltage	VOH	4.7	4.96		V	VDD = 5 V, IOH = -10 mA, VIC = VDD/2, 25°C	5
High-level output voltage	VOH	4.6	4.76		V	VDD = 5 V, IOH = -100 mA, VIC = VDD/2, 25°C	5
High-level output voltage	VOH	4.45	4.6		V	VDD = 5 V, IOH = -200 mA, VIC = VDD/2, 25°C	5
High-level output voltage	VOH	4.35			V	VDD = 5 V, IOH = -200 mA, -40°C to 85°C	5
Low-level output voltage	VOL		0.03	0.1	V	VDD = 3 V and 5 V, IOL = 10 mA, VIC = VDD/2, 25°C	5
Low-level output voltage	VOL		0.33	0.4	V	VDD = 3 V and 5 V, IOL = 100 mA, VIC = VDD/2, 25°C	5
Low-level output voltage	VOL			0.55	V	VDD = 3 V and 5 V, IOL = 100 mA, Full range	5
Low-level output voltage	VOL		0.38	0.6	V	VDD = 5 V, IOL = 200 mA, VIC = VDD/2, 25°C	5
Low-level output voltage	VOL			0.7	V	VDD = 5 V, IOL = 200 mA, -40°C to 85°C	5
Output current	IO		220		mA	Measured at 0.5 V from rail, VDD = 3 V, 25°C (printed ±220)	5
Output current	IO		320		mA	Measured at 0.5 V from rail, VDD = 5 V, 25°C (printed ±320)	5
Short-circuit output current, sourcing	IOS		800		mA	25°C	5
Short-circuit output current, sinking	IOS		800		mA	25°C	5
Supply current (per channel)	IDD		700	1000	µA	VO = VDD/2, 25°C	5
Supply current (per channel)	IDD			1500	µA	VO = VDD/2, Full range	5
Power supply rejection ratio	PSRR	70	82		dB	VDD = 2.7 to 3.3 V, VIC = VDD/2, No load, 25°C	5
Power supply rejection ratio	PSRR	65			dB	VDD = 2.7 to 3.3 V, VIC = VDD/2, No load, Full range	5
Power supply rejection ratio	PSRR	70	79		dB	VDD = 4.5 to 5.5 V, VIC = VDD/2, No load, 25°C	5
Gain bandwidth product	GBWP		2.7		MHz	RL = 100 Ω, CL = 10 pF, 25°C	6
Slew rate at unity gain	SR	0.8	1.57		V/µs	VO(pp) = 2 V, RL = 100 Ω, CL = 10 pF, VDD = 3 V, 25°C	6
Slew rate at unity gain	SR	0.55			V/µs	VDD = 3 V, Full range	6
Slew rate at unity gain	SR	1	1.57		V/µs	VDD = 5 V, 25°C	6
Slew rate at unity gain	SR	0.7			V/µs	VDD = 5 V, Full range	6
Phase margin	φM		66		°	RL = 100 Ω, CL = 10 pF, 25°C	6
Gain margin			16		dB	RL = 100 Ω, CL = 10 pF, 25°C	6
Settling time	ts		0.7		µs	V(STEP)pp = 1 V, AV = -1, CL = 10 pF, RL = 100 Ω, 0.1%, 25°C	6
Settling time	ts		1.3		µs	0.01%, 25°C	6
Total harmonic distortion plus noise	THD+N		0.025		%	VO(pp) = VDD/2 V, RL = 100 Ω, f = 100 Hz, AV = 1	6
Equivalent input noise voltage	Vn		55		nV/√Hz	f = 100 Hz, 25°C	6
Equivalent input noise voltage	Vn		10		nV/√Hz	f = 10 kHz, 25°C	6
Equivalent input noise current	In		0.31		fA/√Hz	f = 1 kHz	6
Supply current in shutdown mode (per channel)	IDD(SHDN)		3.4	10	µA	SHDN = 0 V, 25°C	6
Supply current in shutdown mode (per channel)	IDD(SHDN)			15	µA	SHDN = 0 V, Full range	6

CAD (KiCad official)

Symbol: TLV4110IDR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tlv4110idr-etched.step / tlv4110idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv4110idr.step / tlv4110idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 fbdc43bbddb636fb, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TLV4110IDR

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3D Model

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