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MCP79510T-I
Public Made by Adomby adom
Microchip Tech Real Time Clocks, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP79510T-I
Microchip Tech · Real Time Clocks · MSOP-10
MCP79510T-I from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | X1 | input | Crystal oscillator input for a 32.768 kHz crystal, optimized for 6-9 pF load capacitance, that also serves as the external clock input when the device uses an external oscillator. |
| 2 | X2 | output | Crystal oscillator output for the external 32.768 kHz quartz crystal, which must be left floating when an external clock is driven into X1. |
| 3 | VBAT | power_in | Backup supply input that maintains the RTCC and SRAM during VCC unavailability, with a backup range of 1.3V to 3.6V; VBAT must be connected to VSS if battery backup is not used and VCC should be applied before VBAT. |
| 4 | CS | input | Active-low chip select that selects the device when low and deselects it when high, with a high-to-low transition required after power-up before any sequence is initiated. |
| 5 | VSS | power_in | Ground reference pin for the device. |
| 6 | SI | input | Serial data input that receives instructions, addresses and data, latched on the rising edge of the serial clock. |
| 7 | SO | tri_state | Serial data output that shifts data out after the falling edge of the serial clock during a read cycle and enters the high-impedance state when the device is deselected. |
| 8 | SCK | input | Serial clock input that synchronizes host communication, latching SI on the rising edge and updating SO after the falling edge, with SPI clock rate up to 5 MHz. |
| 9 | MFP | output | Multifunction pin shared with the clock divider and alarms that requires an external pull-up to VCC or VBAT, remains low until the interrupt flag is cleared by software, and has a maximum sink current of 10 mA. |
| 10 | VCC | power_in | Primary power supply with an operating voltage range of 1.8V to 3.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | Clock/Timing |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage VCC | VCC | 1.8 | 3.6 | V | Industrial (I): TA = -40°C to +85°C | 4 | |
| Operating ambient temperature | TA | -40 | 85 | °C | Industrial (I) | 4 | |
| Voltage on all inputs and outputs w.r.t. VSS (lower limit) | -0.6 | V | 4 | ||||
| Storage temperature | -65 | 150 | °C | 4 | |||
| Ambient temperature under bias | -40 | 85 | °C | 4 | |||
| ESD protection on all pins | 4 | kV | 4 | ||||
| High-Level Input Voltage (lower limit, 0.7 VCC) | VIH | 0.7 | VCC | 4 | |||
| High-Level Input Voltage (upper limit, VCC + 1 V) | VIH | 1 | V | 4 | |||
| Low-Level Input Voltage (lower limit, VCC ≥ 2.5V) | VIL | -0.3 | V | VCC ≥ 2.5V | 4 | ||
| Low-Level Input Voltage (upper limit, VCC ≥ 2.5V) | VIL | 0.3 | VCC | VCC ≥ 2.5V | 4 | ||
| Low-Level Input Voltage (lower limit, VCC < 2.5V) | VIL | -0.3 | V | VCC < 2.5V | 4 | ||
| Low-Level Input Voltage (upper limit, VCC < 2.5V) | VIL | 0.2 | VCC | VCC < 2.5V | 4 | ||
| Low-Level Output Voltage | VOL | 0.4 | V | IOL = 2.1 mA, VCC ≥ 2.5V | 4 | ||
| Low-Level Output Voltage | VOL | 0.2 | V | IOL = 1.0 mA, VCC < 2.5V | 4 | ||
| High-Level Output Voltage (offset VCC - 0.5 V) | VOH | -0.5 | V | IOH = -400 µA | 4 | ||
| Input Leakage Current | ILI | -1 | 1 | µA | CS = VCC, VIN = VSS or VCC | 4 | |
| Output Leakage Current | ILO | -1 | 1 | µA | CS = VCC, VOUT = VSS or VCC | 4 | |
| Pin Capacitance (all inputs and outputs) | CINT | 7 | pF | VCC = 3.6V, TA = +25°C, f = 1 MHz | 4 | ||
| EEPROM Operating Current (read) | ICCEERD | 3 | mA | VCC = 3.6V, FCLK = 5 MHz, SO = Open | 4 | ||
| EEPROM Operating Current (write) | ICCEEWR | 5 | mA | VCC = 3.6V | 4 | ||
| SRAM/RTCC Operating Current (read) | ICCREAD | 3 | mA | VCC = 3.6V, FCLK = 5 MHz, SO = Open | 4 | ||
| SRAM/RTCC Operating Current (write) | ICCWRITE | 3 | mA | VCC = 3.6V, FCLK = 5 MHz | 4 | ||
| VCC Data Retention Current (oscillator off) | ICCDAT | 1 | µA | VCC = 3.6V | 4 | ||
| Timekeeping Current | ICCT | 1.2 | µA | VCC = 1.8V, CS = VCC | 4 | ||
| Timekeeping Current | ICCT | 1.2 | 1.8 | µA | VCC = 3.0V, CS = VCC | 4 | |
| Timekeeping Current | ICCT | 2.6 | µA | VCC = 3.6V, CS = VCC | 4 | ||
| Power-Fail Switchover Voltage | VTRIP | 1.3 | 1.5 | 1.7 | V | 5 | |
| Backup Supply Voltage Range | VBAT | 1.3 | 3.6 | V | 5 | ||
| Timekeeping Backup Current | IBATT | 850 | nA | VBAT = 1.3V, VCC = VSS | 5 | ||
| Timekeeping Backup Current | IBATT | 1000 | 1200 | nA | VBAT = 3.0V, VCC = VSS | 5 | |
| Timekeeping Backup Current | IBATT | 2300 | nA | VBAT = 3.6V, VCC = VSS | 5 | ||
| VBAT Data Retention Current (oscillator off) | IBATDAT | 850 | nA | VBAT = 3.6V, VCC = VSS | 5 | ||
| Clock Frequency | FCLK | 5 | MHz | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Clock Frequency | FCLK | 3 | MHz | 1.8V ≤ Vcc < 2.5V | 6 | ||
| CS Setup Time | TCSS | 100 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| CS Setup Time | TCSS | 150 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| CS Hold Time | TCSH | 100 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| CS Hold Time | TCSH | 150 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| CS Disable Time | TCSD | 50 | ns | 6 | |||
| Data Setup Time | TSU | 20 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Data Setup Time | TSU | 30 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| Data Hold Time | THD | 40 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Data Hold Time | THD | 50 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| SCK Rise Time | TR | 100 | ns | Note 1 | 6 | ||
| SCK Fall Time | TF | 100 | ns | Note 1 | 6 | ||
| Clock High Time | THI | 100 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Clock High Time | THI | 150 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| Clock Low Time | TLO | 100 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Clock Low Time | TLO | 150 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| Clock Delay Time | TCLD | 50 | ns | 6 | |||
| Clock Enable Time | TCLE | 50 | ns | 6 | |||
| Output Valid from Clock Low | TV | 100 | ns | 2.5V ≤ Vcc < 3.6V | 6 | ||
| Output Valid from Clock Low | TV | 160 | ns | 1.8V ≤ Vcc < 2.5V | 6 | ||
| Output Disable Time | TDIS | 80 | ns | 2.5V ≤ Vcc < 3.6V (Note 1) | 6 | ||
| Output Disable Time | TDIS | 160 | ns | 1.8V ≤ Vcc < 2.5V (Note 1) | 6 | ||
| Internal Write Cycle Time | TWC | 5 | ms | Note 2 | 6 | ||
| VCC Fall Time | TFVCC | 300 | µs | Note 1 | 6 | ||
| Endurance | 1 | M E/W cycles | Page Mode, +25°C, VCC = 3.6V (Note 1) | 6 | |||
| Oscillator Frequency | FOSC | 32.768 | kHz | 6 |
CAD (KiCad official)
- Symbol:
MCP79510T-I - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
mcp79510t-i-etched.step/mcp79510t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp79510t-i.step/mcp79510t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (58 pp, sha256
1caaeadd97693b59, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).