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DAC082S085CISD
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC082S085CISD
Texas Instruments · Digital To Analog Converters (DACs) · WSON-10-EP(3x3)
DAC082S085CISD from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VA | power_in | Power supply input that must be decoupled to GND. |
| 2 | VOUTA | output | Channel A analog output voltage, rail-to-rail swing per the on-chip output amplifier. |
| 3 | VOUTB | output | Channel B analog output voltage, rail-to-rail swing per the on-chip output amplifier. |
| 4 | NC | unconnected | Not connected. |
| 5 | NC | unconnected | Not connected. |
| 6 | GND | power_in | Ground reference for all on-chip circuitry. |
| 7 | VREFIN | input | Unbuffered reference voltage shared by both channels, which must be decoupled to GND. |
| 8 | DIN | input | Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |
| 9 | SYNC | input | Active-low frame sync that enables the input shift register; the DAC updates on the 16th SCLK falling edge, and a rising edge before the 16th clock aborts the write. |
| 10 | SCLK | input | Serial clock input; data is clocked into the input shift register on its falling edges. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VA | VA | 6.5 | V | Absolute maximum rating | 5 | ||
| Voltage on any input pin | -0.3 | 6.5 | V | Absolute maximum rating | 5 | ||
| Input current at any pin | 10 | mA | Absolute maximum rating | 5 | |||
| Package input current | 20 | mA | Absolute maximum rating | 5 | |||
| Junction temperature | TJ | 150 | °C | Absolute maximum rating | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | Absolute maximum rating | 5 | |
| Operating temperature | TA | -40 | 105 | °C | Operating free-air temperature range | 5 | |
| Supply voltage | VA | 2.7 | 5.5 | V | 5 | ||
| Reference voltage | VREFIN | 1 | V | Maximum printed as VA | 5 | ||
| Digital input voltage | 0 | 5.5 | V | 5 | |||
| Output load | 0 | 1500 | pF | 5 | |||
| SCLK frequency | fSCLK | 40 | MHz | Up to 40 MHz | 5 | ||
| Integral non-linearity | INL | -0.14 | 0.14 | LSB | TA = 25°C | 6 | |
| Integral non-linearity | INL | -0.5 | 0.5 | LSB | TMIN ≤ TA ≤ TMAX | 6 | |
| Differential non-linearity | DNL | -0.02 | 0.04 | LSB | VA = 2.7 V to 5.5 V, TA = 25°C | 6 | |
| Differential non-linearity | DNL | -0.13 | 0.18 | LSB | VA = 2.7 V to 5.5 V, TMIN ≤ TA ≤ TMAX | 6 | |
| Zero code error | ZE | 15 | mV | IOUT = 0, TMIN ≤ TA ≤ TMAX | 6 | ||
| Full-scale error | FSE | -0.75 | %FSR | IOUT = 0, TMIN ≤ TA ≤ TMAX | 6 | ||
| Gain error | GE | -1 | %FSR | All ones loaded to DAC register, TMIN ≤ TA ≤ TMAX | 6 | ||
| Output voltage | 0 | V | TMIN ≤ TA ≤ TMAX; upper limit printed as VREFIN | 6 | |||
| High-impedance output leakage current | IOZ | -1 | 1 | µA | TMIN ≤ TA ≤ TMAX | 6 | |
| Continuous output current | IO | 11 | mA | Available on each DAC output, TMIN ≤ TA ≤ TMAX | 6 | ||
| Maximum load capacitance | CL | 1500 | pF | RL = ∞ | 6 | ||
| VREFIN input range minimum | VREFIN | 1 | V | TMIN ≤ TA ≤ TMAX | 7 | ||
| Input current | IIN | -1 | 1 | µA | TMIN ≤ TA ≤ TMAX | 7 | |
| Input low voltage | VIL | 0.6 | V | VA = 3 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Input low voltage | VIL | 0.8 | V | VA = 5 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Input high voltage | VIH | 2.1 | V | VA = 3 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Input high voltage | VIH | 2.4 | V | VA = 5 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Supply voltage minimum | VA | 2.7 | V | TMIN ≤ TA ≤ TMAX | 7 | ||
| Supply voltage maximum | VA | 5.5 | V | TMIN ≤ TA ≤ TMAX | 7 | ||
| Normal supply current | IN | 270 | µA | fSCLK = 30 MHz, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Normal supply current | IN | 410 | µA | fSCLK = 30 MHz, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Power down supply current | IPD | 1 | µA | All PD modes, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Normal supply power | PN | 1 | mW | fSCLK = 30 MHz, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Normal supply power | PN | 2.3 | mW | fSCLK = 30 MHz, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Power down supply power | PPD | 3.6 | µW | All PD modes, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| Power down supply power | PPD | 5.5 | µW | All PD modes, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX | 7 | ||
| SCLK frequency | fSCLK | 30 | MHz | TMIN ≤ TA ≤ TMAX | 8 | ||
| Output voltage settling time | ts | 4.5 | µs | 40h to C0h code change, RL = 2 kΩ, CL = 200 pF, TMIN ≤ TA ≤ TMAX | 8 | ||
| SCLK cycle time | 1/fSCLK | 25 | ns | TA = 25°C | 8 | ||
| SCLK cycle time | 1/fSCLK | 33 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| SCLK high time | tCH | 7 | ns | TA = 25°C | 8 | ||
| SCLK high time | tCH | 10 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| SCLK low time | tCL | 7 | ns | TA = 25°C | 8 | ||
| SCLK low time | tCL | 10 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| SYNC setup time prior to SCLK falling edge | tSS | 4 | ns | TA = 25°C | 8 | ||
| SYNC setup time prior to SCLK falling edge | tSS | 10 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| Data setup time prior to SCLK falling edge | tDS | 1.5 | ns | TA = 25°C | 8 | ||
| Data setup time prior to SCLK falling edge | tDS | 3.5 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| Data hold time after SCLK falling edge | tDH | 1.5 | ns | TA = 25°C | 8 | ||
| Data hold time after SCLK falling edge | tDH | 3.5 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| SCLK fall prior to rise of SYNC | tCFSR | 3 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| SYNC high time | tSYNC | 10 | ns | TMIN ≤ TA ≤ TMAX | 8 | ||
| Junction-to-ambient thermal resistance | RθJA | 250 | °C/W | DSC (WSON, 10 pins) | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 40.7 | °C/W | DSC (WSON, 10 pins) | 6 | ||
| Junction-to-board thermal resistance | RθJB | 23.7 | °C/W | DSC (WSON, 10 pins) | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bottom) | 4.7 | °C/W | DSC (WSON, 10 pins) | 6 |
CAD (KiCad official)
- Symbol:
DAC082S085CISD - Footprint:
Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac082s085cisd-etched.step/dac082s085cisd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac082s085cisd.step/dac082s085cisd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
5e4a7a26e8484d89, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).