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CDCM6208V2GRGZR

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CDCM6208V2GRGZR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-48-EP(7x7)

CDCM6208V2GRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI_MODE0 input Serial interface or pin mode select bit 0 (LVCMOS input with 50kΩ pull-down); SI_MODE[1:0] = 00 selects SPI, 01 selects I2C, 10 selects pin mode.
2 SDI/SDA/PIN1 bidirectional SPI serial data input (SDI), I2C serial data (SDA, bidirectional open-drain requiring a pull-up in I2C mode), or control pin 1 in pin mode.
3 SDO/AD0/PIN2 bidirectional SPI serial data output (SDO), I2C address offset bit 0 input (AD0), or control pin 2 in pin mode.
4 SCS/AD1/PIN3 input SPI latch enable (SCS), I2C address offset bit 1 input (AD1), or control pin 3 in pin mode (LVCMOS, no pull resistor).
5 SCL/PIN4 input SPI/I2C clock input (SCL) or control pin 4 in pin mode (LVCMOS, no pull resistor).
6 REF_SEL input Manual reference selection for the PLL: REF_SEL low (≤ VIL) selects PRI_REF and high (≥ VIH) selects SEC_REF when Reg 4.12 = 1; 50kΩ pull-up.
7 VDD_PRI_REF power_in Analog supply for the primary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_SEC_REF.
8 PRI_REFP input Universal primary reference input, positive terminal.
9 PRI_REFN input Universal primary reference input, negative terminal.
10 VDD_SEC_REF power_in Analog supply for the secondary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_PRI_REF (if the secondary input buffer is disabled, it may be connected to GND).
11 SEC_REFP input Universal secondary reference input, positive terminal.
12 SEC_REFN input Universal secondary reference input, negative terminal.
13 VDD_Y0_Y1 power_in Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (2 pins).
14 Y0_P output Universal output 0, positive terminal.
15 Y0_N output Universal output 0, negative terminal.
16 Y1_N output Universal output 1, negative terminal.
17 Y1_P output Universal output 1, positive terminal.
18 VDD_Y0_Y1 power_in Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (2 pins).
19 VDD_Y2_Y3 power_in Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (2 pins).
20 Y2_P output Universal output 2, positive terminal.
21 Y2_N output Universal output 2, negative terminal.
22 Y3_N output Universal output 3, negative terminal.
23 Y3_P output Universal output 3, positive terminal.
24 VDD_Y2_Y3 power_in Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (2 pins).
25 Y4_N output Universal output 4, negative terminal.
26 Y4_P output Universal output 4, positive terminal.
27 VDD_Y4 power_in Analog supply for output 4, set to 1.8 V, 2.5 V or 3.3 V.
28 Y5_N output Universal output 5, negative terminal.
29 Y5_P output Universal output 5, positive terminal.
30 VDD_Y5 power_in Analog supply for output 5, set to 1.8 V, 2.5 V or 3.3 V.
31 VDD_Y6 power_in Analog supply for output 6, set to 1.8 V, 2.5 V or 3.3 V.
32 Y6_P output Universal output 6, positive terminal.
33 Y6_N output Universal output 6, negative terminal.
34 VDD_Y7 power_in Analog supply for output 7, set to 1.8 V, 2.5 V or 3.3 V.
35 Y7_P output Universal output 7, positive terminal.
36 Y7_N output Universal output 7, negative terminal.
37 VDD_PLL1 power_in Analog power supply connection for the PLL.
38 VDD_PLL2 power_in Analog power supply for the PLL; sensitive to power supply noise and may be combined with VDD_VCO.
39 VDD_VCO power_in Analog power supply for the PLL/VCO; sensitive to power supply noise and may be combined with VDD_PLL2.
40 REG_CAP passive Regulator capacitor; connect a 10 µF capacitor with ESR below 1 Ω to GND at frequencies above 100 kHz.
41 ELF passive External loop filter pin for the PLL.
42 SYNCN input Active-low synchronization input: outputs synchronize on a low-to-high transition, and SYNCN held low disables all outputs (50kΩ pull-up).
43 PDN input Active-low power-down input (50kΩ pull-up): when low the device is disabled with minimized current, and exiting power-down resets the device and defaults all registers.
44 RESETN/PWR input In SPI/I2C mode, active-low external reset (VIL = reset, registers retained); in pin mode it sets core and I/O supply, 0 = 1.8 V and 1 = 2.5/3.3 V (50kΩ pull-up).
45 STATUS1/PIN0 bidirectional Status output 1 in SPI/I2C modes (LVCMOS) or control pin 0 in pin mode.
46 STATUS0 output LVCMOS status output 0; mapped status signals are selected via register bits (see Table 6).
47 SI_MODE1 input Serial interface or pin mode select bit 1 (LVCMOS input with 50kΩ pull-up); see SI_MODE0 for the mode encoding.
48 DVDD power_in Digital power supply; also the reference supply voltage for all control inputs, which must match the expected control input signal swing.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range -0.5 4.6 V VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD 6
Input Voltage Range CMOS control inputs VIN -0.5 4.6 V CMOS control inputs; upper limit also printed as DVDD+0.5 V 6
Input Voltage Range PRI/SEC inputs 4.6 V PRI/SEC inputs; upper limit also printed as VVDDPRI.SEC+0.5 V 6
Output Voltage Range VOUT -0.5 V Max printed as VYxYy+0.5 V (formula, not a number) 6
Input Current IIN 20 mA 6
Output Current IOUT 50 mA 6
Junction Temperature TJ 125 °C 6
Storage temperature range Tstg -65 150 °C 6
VDD_Yx_Yy Output Supply Voltage VDD_Yx_Yy 1.71 3.465 V NOM printed as 1.8/2.5/3.3 V 7
VDD_PLL1 / VDD_PLL2 Core Analog Supply Voltage VDD_PLL1, VDD_PLL2 1.71 3.465 V NOM printed as 1.8/2.5/3.3 V 7
DVDD Core Digital Supply Voltage DVDD 1.71 3.465 V NOM printed as 1.8/2.5/3.3 V 7
Reference Input Supply Voltage VDD_PRI, VDD_SEC 1.71 3.465 V NOM printed as 1.8/2.5/3.3 V 7
Ambient Temperature TA -40 85 °C 7
Input Voltage (SDA and SCL in I2C mode) VI -0.5 2.45 V DVDD = 1.8 V 7
Input Voltage (SDA and SCL in I2C mode) VI -0.5 3.965 V DVDD = 3.3 V 7
Data Rate (I2C mode) dR 100 400 kbps SDA and SCL in I2C mode; standard and fast mode rates 7
High-level input voltage VIH 0.7 x DVDD SDA and SCL in I2C mode 7
Low-level input voltage VIL 0.3 x DVDD SDA and SCL in I2C mode 7
Total capacitive load for each bus line CBUS_I2C 400 pF I2C bus line 7
Input High Voltage VIH 0.8 x DVDD DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = -40°C to 85°C 9
Input Low Voltage VIL 0.2 x DVDD DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = -40°C to 85°C 9
Input High Current IIH 30 µA DVDD = 3.465V, VIH = 3.465 V (pull-up resistor excluded) 9
Input Low Current IIL -30 µA DVDD = 3.465V, VIL = 0 V 9
Input Edge Rate (PDN, RESETN, SYNCN, REF_SEL) ΔV/ΔT 0.75 V/ns 20% - 80% 9
Output Low Voltage (I2C mode) VOL 0.2 x DVDD IOL = 3mA 9
Reference and Bypass Input Frequency fIN 0.008 200 MHz VDD_PRI/SEC = 1.8 V 9
Reference and Bypass Input Frequency fIN 0.008 250 MHz VDD_PRI/SEC = 3.3 V 9
Reference Input Edge Rate ΔV/ΔT 0.75 V/ns 20% - 80% 9
SE Reference Input Duty Cycle IDC 40 60 % fPRI ≤ 200 MHz 9
SE Reference Input Duty Cycle IDC 43 60 % 200 ≤ fPRI ≤ 250 MHz 9
Reference and Bypass Input Frequency fIN 0.008 250 MHz Differential input 10
Differential Input Voltage Swing, Peak-to-Peak VI 0.2 1.6 VPP VDD_PRI/SEC = 2.5/3.3 V 10
Differential Input Voltage Swing, Peak-to-Peak VI 0.2 1 VPP VDD_PRI/SEC = 1.8 V 10
Input Common Mode Voltage (LVDS) VICM 0.8 1.2 1.5 V LVDS, VDD_PRI/SEC = 1.8/2.5/3.3 V, R4[7:6] = 01, R4.1 = d.c., R4.0 = d.c. 10
Output High Voltage VOH 0.8 x DVDD Status 1, Status 0, and SDO only; IOH = 1 mA 11
Output Low Voltage VOL 0.2 x DVDD IOL = 1 mA 11
3-stat Output High Current IOZH 5 µA DVDD = 3.465 V, VIH = 3.465 V 11
3-stat Output Low Current IOZL -5 µA DVDD = 3.465 V, VIL = 0 V 11
VCO Frequency Range fVCO 2.39 2.55 GHz VDD_PLLx, VDD_VCO = 1.71 V to 3.465 V 11
Output Frequency (fractional output divider) fOUT-F 0.78 250 MHz VDD_Yx_Yy = 2.5/3.3 V 12
Output Frequency (integer output divider) fOUT-F 1.55 250 MHz VDD_Yx_Yy = 2.5/3.3 V 12
Output Frequency Error (fractional output divider) fACC-F -1 1 ppm Fractional Output Divider 12
Output High Voltage (normal mode) VOH 0.8 x VDD_Yx_Yy V VDD_Yx = min to max, IOH = -1 mA 12
Output Low Voltage (normal mode) VOL 0.2 x VDD_Yx_Yy V VDD_Yx = min to max, IOL = 100 µA 12
Output High Voltage (slow mode) VOH 0.7 x VDD_Yx_Yy V VDD_Yx = min to max, IOH = -100 µA 12
Output Low Voltage (slow mode) VOL 0.3 x VDD_Yx_Yy V VDD_Yx = min to max, IOL = 100 µA 12
Output High Current (normal mode) IOH -50 -8 mA VOUT = VDD_Yx_Yy/2 12
Output High Current (slow mode) IOH -45 -5 mA VOUT = VDD_Yx_Yy/2 12
Output Low Current (normal mode) IOL 10 55 mA VOUT = VDD_Yx_Yy/2 12
Output Low Current (slow mode) IOL 5 40 mA VOUT = VDD_Yx_Yy/2 12
Output frequency (integer output divider) fOUT-I 1.55 800 MHz LVPECL, VDD_Yx_Yy = 1.71 V to 3.465 V 13
Differential output voltage /VOD/ /VOD/ 0.6 0.8 1.12 V VDD_Yx_Yy ≥ 2.375 V; 100 Ω diff load AC coupling, fOUT ≤ 250 MHz 13
Output duty cycle ODC 47.5 52.5 % Not in bypass mode 13
Output frequency (integer output divider) fOUT-I 1.55 400 MHz LVDS 14
Differential output voltage /VOD/ 0.247 0.34 0.454 V 100 Ω diff load AC coupling 14
Output Common Mode Voltage / Differential Output Voltage /VOD/ 0.4 0.67 1 V HCSL, VDD_Yx_Yy = 2.5/3.3 V 14
Output Rise/Fall Time (HCSL) tR/tF 100 167 250 ps Measured from VDIFF = -100 mV to +100 mV, VDD_Yx_Yy = 2.5/3.3 V 14
Thermal resistance, junction-to-ambient (RθJA) RθJA 30.27 °C/W Airflow = 0 LFM; JESD 51, JEDEC 2S2P high-k board; 36 thermal vias 7
Thermal resistance, junction-to-board (RθJB) RθJB 6.83 °C/W Airflow = 0 LFM; junction to GND pad 7
Thermal resistance, junction-to-case bottom (RθJC(bot)) RθJC(bot) 1.06 °C/W Airflow = 0 LFM 7

CAD (KiCad official)

  • Symbol: CDCM6208V2GRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: cdcm6208v2grgzr-etched.step / cdcm6208v2grgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm6208v2grgzr.step / cdcm6208v2grgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 c0a705671fd73450, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF