component
SG3525N
Public Made by Adomby adom
HGSEMI AC-DC Controllers And Regulators, DIP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownSG3525N
HGSEMI · AC-DC Controllers And Regulators · DIP-16
SG3525N from HGSEMI, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Inv. Input | input | Inverting input of the error amplifier; the 5.1V reference lies within the amplifier's common-mode range so no external divider is needed for it. |
| 2 | Noninv. Input | input | Non-inverting input of the error amplifier, with input common-mode range of 1.5 to 5.2V. |
| 3 | Sync | input | Oscillator synchronization input allowing external clock sync, with sync threshold of 1.2 to 2.8V (2V typical). |
| 4 | OSC. Output | output | Oscillator output providing the clock signal, with typical clock amplitude of 3V min to 4V. |
| 5 | CT | passive | Timing capacitor connection that sets the oscillator frequency together with RT, within a 100Hz to 500kHz range. |
| 6 | RT | passive | Timing resistor connection that sets the oscillator frequency together with CT. |
| 7 | Discharge | passive | Oscillator discharge terminal; the resistor between CT and this pin adjusts the dead time. |
| 8 | Soft-Start | passive | Soft-start capacitor connection driven by a 50µA (51µA typical) internal current source. |
| 9 | Compensation | bidirectional | Error amplifier output for loop compensation, feeding the PWM comparator. |
| 10 | Shutdown | input | Shutdown input that turns off the outputs, with a threshold of 0.6 to 1.0V (0.8V typical). |
| 11 | Output A | output | Totem-pole output A (NOR logic, low in the off state), sourcing and sinking over 150mA. |
| 12 | Ground | power_in | Ground reference for the device. |
| 13 | VC | power_in | Collector supply voltage for the output stage, rated to 40V maximum. |
| 14 | Output B | output | Totem-pole output B (NOR logic, low in the off state), sourcing and sinking over 150mA. |
| 15 | VCC | power_in | Supply voltage input, operating range 8 to 35V with 40V absolute maximum. |
| 16 | Vref | power_out | 5.1V reference output (±1%), with maximum reference output current of 50mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (operating voltage range) | 8 | 35 | V | 1 | |||
| Operating temperature | Top | 0 | 70 | ℃ | 2 | ||
| Supply voltage | Vi | 40 | V | 2 | |||
| Collector supply voltage | VC | 40 | V | 2 | |||
| Oscillator charging current | IOSC | 5 | mA | 2 | |||
| Output source current | Io | 400 | mA | 2 | |||
| Reference output current | IR | 50 | mA | 2 | |||
| Power dissipation | Ptot | 1000 | mW | Tamb= 70°C | 2 | ||
| Junction temperature range | Tj | -55 | 150 | ℃ | 2 | ||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 2 | ||
| Reference output voltage | VREF | 5 | 5.1 | 5.2 | V | TJ = 25℃ | 3 |
| Line regulation | ∆ VREF | 9 | 20 | mV | VCC = 8 to 35V | 3 | |
| Load regulation | ∆ VREF | 20 | 50 | mV | IREF = 0 to 20mA | 3 | |
| Short-circuit output current | ISC | 80 | 100 | mA | VREF = 0, TJ = 25℃ | 3 | |
| Total output variation (line, load and temperature) | ∆ VREF | 4.95 | 5.25 | V | 3 | ||
| Temperature stability | STT | 20 | 50 | mV | 3 | ||
| Long-term stability | ST | 20 | 50 | mV | TJ = 125℃, 1 KHRS | 3 | |
| Initial accuracy | ACCUR | 3 | 6 | % | TJ = 25℃ | 3 | |
| Frequency variation with voltage | ∆ f/∆ VCC | 0.8 | 2 | % | VCC = 8 to 35V | 3 | |
| Maximum frequency | f(MAX) | 400 | 430 | KHz | RT = 2KΩ, CT = 470pF | 3 | |
| Minimum frequency | f(MIN) | 60 | 120 | Hz | RT = 200KΩ, CT = 0.1uF | 3 | |
| Clock amplitude | V(CLK) | 3 | 4 | V | 3 | ||
| Clock width | tW(CLK) | 0.3 | 0.6 | 1 | us | TJ = 25℃ | 3 |
| Synchronization threshold voltage | VTH(SYNC) | 1.2 | 2 | 2.8 | V | 3 | |
| Synchronization input current | II(SYNC) | 1.3 | 2.5 | mA | Sync = 3.5V | 3 | |
| Input offset voltage | VIO | 1.5 | 10 | mV | 3 | ||
| Input bias current | IBIAS | 1 | 10 | µA | 3 | ||
| Input offset current | IIO | 0.1 | 1 | µA | 3 | ||
| Open-loop voltage gain | GVO | 60 | 80 | dB | RL ≥ 10MΩ | 3 | |
| Common-mode rejection ratio | CMRR | 60 | 90 | dB | VCM = 1.5 to 5.2V | 3 | |
| Power supply rejection ratio | PSRR | 50 | 60 | dB | VCC = 8 to 3.5V | 3 | |
| Minimum duty cycle | D(MIN) | 0 | % | 3 | |||
| Maximum duty cycle | D(MAX) | 45 | 49 | % | 3 | ||
| Input threshold voltage at zero duty cycle | VTH1 | 0.7 | 0.9 | V | Zero duty cycle | 3 | |
| Input threshold voltage at maximum duty cycle | VTH2 | 3.2 | 3.6 | V | Maximum duty cycle | 3 | |
| Soft-start current | ISOFT | 25 | 51 | 80 | µA | VSD = 0V, VSS = 0V | 3 |
| Soft-start low level voltage | VSL | 0.3 | 0.7 | V | VSD = 25V | 3 | |
| Shutdown threshold voltage | VTH(SD) | 0.6 | 0.8 | 1 | V | 3 | |
| Shutdown input current | IN(SD) | 0.3 | 1 | mA | VSD = 2.5V | 3 | |
| Low output voltage I | VOL I | 0.1 | 0.4 | V | ISINK = 20mA | 3 | |
| Low output voltage II | VOL II | 0.05 | 2 | V | ISINK = 100mA | 3 | |
| High output voltage I | VOH I | 18 | 19 | V | ISOURCE = 20mA | 3 | |
| High output voltage II | VOH II | 17 | 18 | V | ISOURCE = 100mA | 3 | |
| Undervoltage lockout threshold | VUV | 6 | 7 | 8 | V | V8 and V9 = High | 4 |
| Collector leakage current | ILKG | 80 | 200 | µA | VCC = 35V | 4 | |
| Rise time | tR | 80 | 600 | ns | CL = 1uF, TJ = 25℃ | 4 | |
| Fall time | tF | 70 | 300 | ns | CL = 1uF, TJ = 25℃ | 4 | |
| Supply current | ICC | 12 | 20 | mA | VCC = 35V | 4 |
CAD (KiCad official)
- Symbol:
SG3525N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
sg3525n-etched.step/sg3525n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sg3525n.step/sg3525n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (6 pp, sha256
73f1f5a84d20bdb8, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).