component
CS5526-BSZ
Public Made by Adomby adom
Cirrus Logic Analog To Digital Converters (ADCs), SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCS5526-BSZ
Cirrus Logic · Analog To Digital Converters (ADCs) · SSOP-20-208mil
CS5526-BSZ from Cirrus Logic, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground; the device should be placed over an analog ground plane with AGND connected to that plane. |
| 2 | VA+ | power_in | Positive analog power supply, nominally +5 V. |
| 3 | AIN+ | input | Positive differential analog input to the 20X instrumentation amplifier. |
| 4 | AIN- | input | Negative differential analog input; the unipolar and bipolar offset definitions are referenced to the voltage on this pin. |
| 5 | NBV | power_in | Negative bias voltage supply for the 20X instrumentation amplifier, tied to AGND for inputs centered at +2.5 V or to a negative supply (about -2.1 V typical) to handle signals below ground. |
| 6 | A0 | output | Logic output that mirrors configuration register bit D20, reading AGND for logic 0 and VA+ for logic 1. |
| 7 | A1 | output | Logic output that mirrors configuration register bit D21, reading AGND for logic 0 and VA+ for logic 1. |
| 8 | CPD | output | Square-wave output that supplies energy to the external charge pump. |
| 9 | XIN | input | Crystal input for the master clock, or an external CMOS-compatible clock input; the pin is very high impedance with a crystal, so the trace should be kept short. |
| 10 | XOUT | output | Crystal output of the on-chip clock gate, used with a crystal to form the master clock. |
| 11 | SCLK | input | Serial clock input with Schmitt-trigger behavior that clocks SDI/SDO data and is recognized only when CS is low. |
| 12 | DGND | power_in | Digital ground connection. |
| 13 | VD+ | power_in | Positive digital supply, nominally +3.0 V or +5 V. |
| 14 | SDO | tri_state | Serial data output that goes to high impedance when CS = 1. |
| 15 | A2 | output | Logic output that mirrors configuration register bit D22, reading AGND for logic 0 and VA+ for logic 1. |
| 16 | A3 | output | Logic output that mirrors configuration register bit D23, reading AGND for logic 0 and VA+ for logic 1. |
| 17 | SDI | input | Serial data input whose data is clocked in at the rate set by SCLK. |
| 18 | CS | input | Active-low chip select that enables the serial port; SCLK is recognized only while CS is low, and CS should change only when SCLK = 0. |
| 19 | VREF- | power_in | Negative side of the fully differential voltage reference input for the on-chip modulator. |
| 20 | VREF+ | power_in | Positive side of the fully differential voltage reference input for the on-chip modulator. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cirrus Logic |
| Package | SSOP-20-208mil |
| Category | Data Converters |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Linearity Error | -0.0015 | 0.0007 | 0.0015 | %FS | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV | 2 | |
| No Missing Codes | 20 | Bits | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV | 2 | |||
| Bipolar Offset | -32 | 16 | 32 | LSB | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV; Note 3 | 2 | |
| Unipolar Offset | -64 | 32 | 64 | LSB | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV; Note 3 | 2 | |
| Bipolar Gain Error | -31 | 8 | 31 | ppm | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV | 2 | |
| Unipolar Gain Error | -62 | 16 | 62 | ppm | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV | 2 | |
| Gain Drift | 1 | 3 | ppm/°C | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV; Note 4 | 2 | ||
| Voltage Reference Input Range | (VREF+) - (VREF-) | 1 | 2.5 | 3 | V | TA=25°C; VA+,VD+=5 V ±5%; VREF+=2.5 V, VREF-=AGND; NBV=-2.1 V; FCLK=32.768 kHz; OWR=15 Sps; Bipolar, ±100 mV | 2 |
| Analog Input Common Mode + Signal (NBV = -1.8 to -2.5 V) | -0.15 | 0.95 | V | NBV = -1.8 to -2.5 V; Range = 25 mV, 55 mV, or 100 mV; Bipolar/Unipolar Mode | 3 | ||
| Analog Input Common Mode + Signal (NBV = AGND) | 1.85 | 2.65 | V | NBV = AGND; Range = 25 mV, 55 mV, or 100 mV; Bipolar/Unipolar Mode | 3 | ||
| Full-scale Calibration Range 25 mV | 17.5 | 32.5 | mV | Bipolar/Unipolar Mode; Note 9 | 3 | ||
| Full-scale Calibration Range 55 mV | 38.5 | 71.5 | mV | Bipolar/Unipolar Mode; Note 9 | 3 | ||
| Full-scale Calibration Range 100 mV | 70 | 105 | mV | Bipolar/Unipolar Mode; Note 9 | 3 | ||
| Full-scale Calibration Range 1 V | 0.7 | 1.3 | V | Bipolar/Unipolar Mode; Note 9 | 3 | ||
| Full-scale Calibration Range 2.5 V | 1.75 | 3.25 | V | Bipolar/Unipolar Mode; Note 9 | 3 | ||
| Full-scale Calibration Range 5 V | 3.5 | V | Bipolar/Unipolar Mode; Note 9 | 3 | |||
| Offset Calibration Range 25 mV | -12.5 | 12.5 | mV | Bipolar/Unipolar Mode | 3 | ||
| Offset Calibration Range 55 mV | -27.5 | 27.5 | mV | Bipolar/Unipolar Mode | 3 | ||
| Offset Calibration Range 100 mV | -50 | 50 | mV | Bipolar/Unipolar Mode; Note 10 | 3 | ||
| Offset Calibration Range 1 V | -0.5 | 0.5 | V | Bipolar/Unipolar Mode | 3 | ||
| Offset Calibration Range 2.5 V | -1.25 | 1.25 | V | Bipolar/Unipolar Mode | 3 | ||
| Offset Calibration Range 5 V | -2.5 | 2.5 | V | Bipolar/Unipolar Mode | 3 | ||
| DC Power Supply Current IA+ (Normal Mode) | IA+ | 1.65 | 2.2 | mA | Normal mode | 3 | |
| DC Power Supply Current ID+ (Normal Mode) | ID+ | 15 | 30 | µA | Normal mode | 3 | |
| DC Power Supply Current INBV (Normal Mode) | INBV | 475 | 700 | µA | Normal mode | 3 | |
| Power Consumption Normal Mode | 9.4 | 12.7 | mW | Normal mode; Note 11 | 3 | ||
| Power Consumption Low Power Mode | 4.9 | 8.5 | mW | Low power mode; Note 11 | 3 | ||
| Low-level Input Voltage (All Pins Except XIN and SCLK) | VIL | 0.8 | V | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| Low-level Input Voltage (XIN) | VIL | 0 | 1.5 | V | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | |
| Low-level Input Voltage (SCLK) | VIL | 0.6 | V | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| High-level Input Voltage (XIN) | VIH | 3.5 | V | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| Low-level Output Voltage (All Pins Except CPD and SDO) | VOL | 0.4 | V | Iout = 1.6 mA; TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| Low-level Output Voltage (CPD) | VOL | 0.4 | V | Iout = 2 mA; TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| Low-level Output Voltage (SDO) | VOL | 0.4 | V | Iout = 5.0 mA; TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | ||
| Input Leakage Current | Iin | -10 | 1 | 10 | µA | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 |
| 3-state Leakage Current | IOZ | -10 | 10 | µA | TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0; Notes 2, 12 | 4 | |
| Positive Digital Supply Voltage | VD+ | 2.7 | 5 | 5.25 | V | 5 | |
| Positive Analog Supply Voltage | VA+ | 4.75 | 5 | 5.25 | V | 5 | |
| Analog Reference Voltage (VREF+) - (VREF-) | VRefdiff | 1 | 2.5 | 3 | V | 5 | |
| Negative Bias Voltage | NBV | -1.8 | -2.1 | -2.5 | V | 5 | |
| Positive Digital Supply (absolute) | VD+ | -0.3 | 6 | V | Note 15 | 5 | |
| Positive Analog Supply (absolute) | VA+ | -0.3 | 6 | V | Note 15 | 5 | |
| Negative Bias Voltage (absolute) | NBV | 0.3 | -3 | V | Negative Potential; Note 15 | 5 | |
| Input Current, Any Pin Except Supplies | IIN | -10 | 10 | mA | Notes 16, 17 | 5 | |
| Output Current | IOUT | -25 | 25 | mA | 5 | ||
| Power Dissipation | PDN | 500 | mW | Note 18 | 5 | ||
| Ambient Operating Temperature | TA | -40 | 85 | °C | 5 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 5 | ||
| Master Clock Frequency (Internal Clock) | XIN | 30 | 32.768 | 36 | kHz | Internal clock; Note 19; TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 |
| Master Clock Frequency (External Clock) | XIN | 30 | 32.768 | 100 | kHz | External clock; Note 19; TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 |
| Master Clock Duty Cycle | 40 | 60 | % | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| Serial Clock Frequency | SCLK | 0 | 2 | MHz | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | |
| SCLK Falling to CS Falling (continuous running SCLK) | t0 | 100 | ns | Continuous running SCLK (Note 22); TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| Serial Clock Pulse Width High | t1 | 250 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| Serial Clock Pulse Width Low | t2 | 250 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| CS Enable to Valid Latch Clock (SDI write) | t3 | 50 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| Data Set-up Time prior to SCLK rising (SDI write) | t4 | 50 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| Data Hold Time after SCLK Rising (SDI write) | t5 | 100 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| SCLK Falling Prior to CS Disable (SDI write) | t6 | 100 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 | ||
| CS to Data Valid (SDO read) | t7 | 150 | ns | TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; CL = 50 pF | 6 |
CAD (KiCad official)
- Symbol:
CS5526-BSZ - Footprint:
Package_SO:SSOP-20_5.3x7.2mm_P0.65mm - 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
- 3D model files:
cs5526-bsz-etched.step/cs5526-bsz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs5526-bsz.step/cs5526-bsz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cirrus Logic datasheet (30 pp, sha256
9a25cf391b45f080, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).