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74ACT11000DR

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Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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74ACT11000DR

Texas Instruments · Logic Gates · SOIC-16

74ACT11000DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
2 1Y output Output of NAND gate 1, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL).
3 2Y output Output of NAND gate 2, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL).
4 GND power_in Ground reference for the device; one of two GND pins that should both be connected.
5 GND power_in Ground reference for the device; one of two GND pins that should both be connected.
6 3Y output Output of NAND gate 3, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL).
7 4Y output Output of NAND gate 4, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL).
8 4B input Input B of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
9 4A input Input A of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
10 3B input Input B of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
11 3A input Input A of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
12 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected.
13 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected.
14 2B input Input B of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
15 2A input Input A of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.
16 1B input Input B of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: 74ACT11000DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74act11000dr-etched.step / 74act11000dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74act11000dr.step / 74act11000dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (10 pp, sha256 12ce66baa18c48d4, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF