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DSPIC33CK1024MP706-E

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Microchip Tech Digital Signal Processors (DSP/DSC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersdspic33ck1024mp706-efactory-2.0.0extractor-text

Verified DSPIC33CK1024MP706-E

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DSPIC33CK1024MP706-E · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 1127-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rt55giic/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dspic33ck1024mp706-e.kicad_sym✓ dspic33ck1024mp706-e.kicad_mod✓ dspic33ck1024mp706-e.step
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3D Model

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Symbol & Footprint

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Contents

README

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DSPIC33CK1024MP706-E

Microchip Tech · Digital Signal Processors (DSP/DSC) · TQFP-64(10x10)

DSPIC33CK1024MP706-E from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RB14 bidirectional RB14 I/O, multiplexed with RP46/PWM1H/PMD5; 5.5 V tolerant.
2 RB15 bidirectional RB15 I/O, multiplexed with RP47/PWM1L/PMD6; 5.5 V tolerant.
3 RC12 bidirectional RC12 I/O, multiplexed with RP60/PWM8H/PMD7; 5.5 V tolerant.
4 RC13 bidirectional RC13 I/O, multiplexed with RP61/PWM8L/PMA5; 5.5 V tolerant.
5 RC14 bidirectional RC14 I/O, multiplexed with RP62/PWM6H/PMA4; 5.5 V tolerant.
6 RC15 bidirectional RC15 I/O, multiplexed with RP63/PWM6L/PMA3; 5.5 V tolerant.
7 MCLR input Master Clear (active-low Reset) input, also used for device programming and debugging; 5.5 V tolerant.
8 RD15 bidirectional RD15 I/O, multiplexed with RP79/PCI22/PMA2; 5.5 V tolerant.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDD power_in Positive supply for peripheral logic and I/O pins.
11 RD14 bidirectional RD14 I/O, multiplexed with RP78/PCI21; 5.5 V tolerant.
12 RD13 bidirectional RD13 I/O, multiplexed with ANN4/CMP5B/RP77.
13 RC0 bidirectional RC0 I/O, multiplexed with AN12/ANN0/RP48.
14 RA0 bidirectional RA0 I/O, multiplexed with OA1OUT/AN0/CMP1A/IBIAS0.
15 RA1 bidirectional RA1 I/O, multiplexed with OA1IN-/ANA1.
16 RA2 bidirectional RA2 I/O, multiplexed with OA1IN+/AN9/PMA6.
17 RA3 bidirectional RA3 I/O, multiplexed with DACOUT1/AN3/AN31/CMP1C.
18 RA4 bidirectional RA4 I/O, multiplexed with OA3OUT/AN4/ANB1/ANB2/CMP3B/IBIAS3.
19 AVDD power_in Positive supply for analog modules; must be connected at all times.
20 AVSS power_in Ground reference for analog modules; must be connected at all times.
21 RD12 bidirectional RD12 I/O, multiplexed with RP76; 5.5 V tolerant.
22 RC1 bidirectional RC1 I/O, multiplexed with OA3IN-/AN13/CMP1B/ISRC0/RP49/PMA7.
23 RC2 bidirectional RC2 I/O, multiplexed with OA3IN+/AN14/CMP2B/ISRC1/RP50/PMD13/PMA13.
24 RC6 bidirectional RC6 I/O, multiplexed with AN17/ANN1/CMP4B/IBIAS1/RP54/PMD12/PMA12.
25 VDD power_in Positive supply for peripheral logic and I/O pins.
26 VSS power_in Ground reference for logic and I/O pins.
27 RC3 bidirectional RC3 I/O, multiplexed with AN15/ANN2/CMP2A/IBIAS2/RP51/PMD11/PMA11.
28 RB0 bidirectional RB0 I/O, multiplexed with OSCI/CLKI/AN5/RP32/PMD10/PMA10; primary oscillator input.
29 RB1 bidirectional RB1 I/O, multiplexed with OSCO/CLKO/AN6/RP33/PMA1/PMALH/PSA1; primary oscillator output, toggled during programming.
30 RD11 bidirectional RD11 I/O, multiplexed with AN19/ANB0/CMP2C/RP75/PMA0/PMALL/PSA0.
31 RD10 bidirectional RD10 I/O, multiplexed with AN18/ANC2/CMP3C/ISRC3/RP74/PMD9/PMA9.
32 RC7 bidirectional RC7 I/O, multiplexed with DACOUT2/AN16/CMP4C/ISRC2/RP55/PMD8/PMA8.
33 RB2 bidirectional RB2 I/O, multiplexed with OA2OUT/AN1/AN7/ANA0/ANA2/ANA3/CMP1D-CMP6D/RP34/SCL3/INT0.
34 RB3 bidirectional RB3 I/O, multiplexed with PGD2/OA2IN-/AN8/CMP4A/RP35; ICSP data channel 2.
35 RB4 bidirectional RB4 I/O, multiplexed with PGC2/OA2IN+/RP36; ICSP clock channel 2.
36 RC8 bidirectional RC8 I/O, multiplexed with RP56/ASDA1/SCK2; 5.5 V tolerant.
37 RC9 bidirectional RC9 I/O, multiplexed with RP57/ASCL1/SDI2; 5.5 V tolerant.
38 RD9 bidirectional RD9 I/O, multiplexed with RP73/PCI20; 5.5 V tolerant.
39 RD8 bidirectional RD8 I/O, multiplexed with RP72/SDO2/PCI19; 5.5 V tolerant.
40 VSS power_in Ground reference for logic and I/O pins.
41 VDD power_in Positive supply for peripheral logic and I/O pins.
42 RD7 bidirectional RD7 I/O, multiplexed with RP71/PMD15; 5.5 V tolerant.
43 RD6 bidirectional RD6 I/O, multiplexed with RP70/PMD14; 5.5 V tolerant.
44 RD5 bidirectional RD5 I/O, multiplexed with RP69/PMA15/PMCS2; 5.5 V tolerant.
45 RB5 bidirectional RB5 I/O, multiplexed with PGD3/RP37/SDA2/PMA14/PMCS1/PSCS; ICSP data channel 3, 5.5 V tolerant.
46 RB6 bidirectional RB6 I/O, multiplexed with PGC3/RP38/SCL2; ICSP clock channel 3, 5.5 V tolerant.
47 RB7 bidirectional RB7 I/O, multiplexed with TDO/AN2/AN30/CMP3A/RP39/SDA3; JTAG test data output.
48 RB8 bidirectional RB8 I/O, multiplexed with PGD1/AN10/CMP6A/RP40/SCL1; ICSP data channel 1.
49 RB9 bidirectional RB9 I/O, multiplexed with PGC1/AN11/CMP5A/RP41/SDA1; ICSP clock channel 1.
50 RC4 bidirectional RC4 I/O, multiplexed with RP52/PWM5H/ASDA2; 5.5 V tolerant.
51 RC5 bidirectional RC5 I/O, multiplexed with RP53/PWM5L/ASCL2/PMWR/PMENB/PSWR; 5.5 V tolerant.
52 RC10 bidirectional RC10 I/O, multiplexed with RP58/PWM7H/PMRD/PMWR/PSRD; 5.5 V tolerant.
53 RC11 bidirectional RC11 I/O, multiplexed with RP59/PWM7L; 5.5 V tolerant.
54 RD4 bidirectional RD4 I/O, multiplexed with RP68/ASDA3; 5.5 V tolerant.
55 RD3 bidirectional RD3 I/O, multiplexed with RP67/ASCL3; 5.5 V tolerant.
56 VSS power_in Ground reference for logic and I/O pins.
57 VDD power_in Positive supply for peripheral logic and I/O pins.
58 RD2 bidirectional RD2 I/O, multiplexed with RP66; 5.5 V tolerant.
59 RD1 bidirectional RD1 I/O, multiplexed with RP65/PWM4H; 5.5 V tolerant.
60 RD0 bidirectional RD0 I/O, multiplexed with RP64/PWM4L/PMD0; 5.5 V tolerant.
61 RB10 bidirectional RB10 I/O, multiplexed with TMS/RP42/PWM3H/PMD1; JTAG test mode select, pull-up connected when device is erased and during programming; 5.5 V tolerant.
62 RB11 bidirectional RB11 I/O, multiplexed with TCK/RP43/PWM3L/PMD2; JTAG test clock; 5.5 V tolerant.
63 RB12 bidirectional RB12 I/O, multiplexed with TDI/RP44/PWM2H/PMD3; JTAG test data input; 5.5 V tolerant.
64 RB13 bidirectional RB13 I/O, multiplexed with RP45/PWM2L/PMD4; 5.5 V tolerant.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3 3.6 V DC10 1052
Analog Supply Voltage (greater of VDD-0.3 or 3.0 / lesser of VDD+0.3 or 3.6) AVDD 3 3.6 V Difference between AVDD and VDD must not exceed ±300 mV at all times, including power-up 1052
Operating Ambient Temperature Range (Extended) TA -40 125 °C Extended Temperature Devices 1052
Operating Junction Temperature Range (Extended) TJ -40 150 °C Extended Temperature Devices 1052
Maximum MIPS 100 MIPS 3.0V to 3.6V, -40°C to +125°C 1051
Voltage on VDD with respect to VSS VDD -0.3 4 V 1051
Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 V Max (VDD + 0.3V) 1051
Voltage on any 5V tolerant pin with respect to VSS -0.3 5.5 V VDD ≥ 3.0V 1051
Voltage on any 5V tolerant pin with respect to VSS -0.3 3.6 V VDD < 3.0V 1051
Ambient temperature under bias -40 125 °C 1051
Storage temperature -65 150 °C 1051
Maximum current out of VSS pin 300 mA 1051
Maximum current into VDD pin 300 mA 1051
Maximum current sunk/sourced by any 4x I/O pin 15 mA 1051
Maximum current sunk/sourced by any 8x I/O pin 25 mA 1051
Maximum current sunk by a group of I/Os between two VSS pins 75 mA Not applicable to AVDD and AVSS pins 1051
Maximum current sourced by a group of I/Os between two VDD pins 75 mA Not applicable to AVDD and AVSS pins 1051
Maximum current sunk by all ports 200 mA 1051
BOR Event on VDD Transition High-to-Low VBOR 2.68 2.84 2.99 V BO10 1053
VDD Rise Rate to Ensure Internal Power-on Reset Signal SVDD 0.03 V/ms 0V-3V in 100 ms 1053
VDD Start Voltage to Ensure Internal Power-on Reset Signal VPOR 0 V DC16, printed as VSS 1053
Input Low Voltage, Any I/O Pin and MCLR VIL 0 0.2 V Min VSS, max 0.2 VDD (value in VDD fraction) 1059
Input Low Voltage, I/O Pins with SDAx, SCLx VIL 0 0.3 V SMBus disabled; min VSS, max 0.3 VDD 1059
Input Low Voltage, I/O Pins with SDAx, SCLx VIL 0 0.8 V SMBus enabled 1059
Input High Voltage, I/O Pins Not 5V Tolerant VIH 0.8 V Min 0.8 VDD, max VDD (value in VDD fraction) 1060
Input High Voltage, 5V Tolerant I/O Pins and MCLR VIH 0.8 5.5 V Min 0.8 VDD 1060
Input High Voltage, 5V Tolerant I/O Pins with SDAx, SCLx VIH 2.1 5.5 V SMBus enabled 1060
Input High Voltage, 5V Tolerant I/O Pins with SDAx, SCLx VIH 1.35 5.5 V SMBus 3.0 1060
Input Change Notification Pull-up Current ICNPU 175 360 545 µA VDD = 3.6V, VPIN = VSS 1060
Input Change Notification Pull-Down Current ICNPD 65 215 360 µA VDD = 3.6V, VPIN = VDD 1060
Input Leakage Current, I/O Pins 5V Tolerant IIL -700 700 nA VPIN = VSS or VDD 1060
Input Leakage Current, MCLR IIL -700 700 nA 1060
Input Leakage Current, OSCI IIL -700 700 nA XT and HS modes 1060
Input Low Injection Current IICL -5 mA All pins; printed min 0, max -5 1060
PLL VCO Input Frequency Range FPLLI 8 64 MHz ECPLL, XTPLL modes 1065
PLL On-Chip VCO System Frequency FVCO 400 1600 MHz 1065
APLL VCO Input Frequency Range FPLLI 8 64 MHz ECPLL, XTPLL modes 1065
APLL On-Chip VCO System Frequency FVCO 400 1600 MHz 1065
Operating Current (IDD), 100 MIPS IDD 31.79 42.5 mA +125°C 3.3V 100 MIPS (FPLLO = 400 MHz) 1054
Operating Current (IDD), 100 MIPS IDD 26.29 30.1 mA +25°C 3.3V 100 MIPS (FPLLO = 400 MHz) 1054
Operating Current (IDD), 10 MIPS IDD 12.95 23.5 mA +125°C 3.3V 10 MIPS (FPLLO = 40 MHz) 1054
Idle Current (IIDLE), 100 MIPS IIDLE 19.56 30 mA +125°C 3.3V 100 MIPS 1055
Power-Down Current (IPD), Sleep IPD 498 1800 µA +25°C 3.3V 1056
Power-Down Current (IPD), Sleep IPD 8.2 20.1 mA +125°C 3.3V 1056
Doze Current (IDOZE), 100 MIPS, 1:2 IDOZE 25.79 36.5 mA +125°C 3.3V 100 MIPS 1056
Watchdog Timer Delta Current ΔIWDT 100 600 µA +125°C 3.3V 1057
PWM Delta Current 5.47 7 mA +125°C, 3.3V PWM Output 500 kHz, AFPLLO = 500 MHz 1057
APLL Delta Current 7.15 9 mA +125°C, 3.3V AFPLLO = 500 MHz 1058
ADC Delta Current 3.89 4.6 mA +125°C 3.3V TAD = 14.3 ns (3.5 Msps) 1058
Comparator + DAC Delta Current 1.24 1.65 mA +125°C, 3.3V AFPLLO @ 500 MHz 1059
Op Amp Delta Current 0.4647 1.7 mA +125°C 3.3V 1059
POR Event on VDD Transition High-to-Low VPOR 1.65 V VDD (Notes 2, 3) 1053
PLL Start-up Time (Lock Time) TLOCK 60 µs 1065
APLL Start-up Time (Lock Time) TLOCK 125 µs 1065
Package Thermal Resistance, 64-Pin TQFP, 10x10x1 mm θJA 45.7 °C/W Junction to ambient, by package simulation 1052

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pou 32

CAD (KiCad official)

  • Symbol: DSPIC33CK1024MP706-E
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: dspic33ck1024mp706-e-etched.step / dspic33ck1024mp706-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ck1024mp706-e.step / dspic33ck1024mp706-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1127 pp, sha256 8aa1f585b06d3129, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF