component
TPS75418QPWPR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS75418QPWPR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP
TPS75418QPWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 2 | NC | unconnected | Not connected. |
| 3 | IN | power_in | Input voltage; absolute maximum VIN is -0.3 V to +6 V, and an input bypass capacitor of 0.22 µF to 1 µF should be placed as close to the input pins as possible. |
| 4 | IN | power_in | Input voltage; absolute maximum VIN is -0.3 V to +6 V, and an input bypass capacitor of 0.22 µF to 1 µF should be placed as close to the input pins as possible. |
| 5 | EN | input | Enable input: a logic low enables the device and a logic high shuts it down; the absolute maximum voltage at EN is -0.3 V to +16.5 V. |
| 6 | RESET/PG | output | Open-drain active-high power-good (PG) output on the TPS754xxQ, which goes high-impedance when VOUT reaches 83% of its regulated voltage and requires an external pullup resistor; absolute maximum PG voltage is 16.5 V. |
| 7 | FB/SENSE | input | Feedback input for the adjustable version (connected to an external resistor divider, Vref 1.1834 V) and sense input for fixed-output versions, which must be connected as short as possible to the regulator output; the absolute maximum voltage at OUT and FB is 5.5 V. |
| 8 | OUTPUT | power_out | Regulated output voltage with 2% tolerance over specified line, load and temperature; the output needs at least 47 µF with ESR between 100 mΩ and 10 Ω, and peak output current is internally limited. |
| 9 | OUTPUT | power_out | Regulated output voltage with 2% tolerance over specified line, load and temperature; the output needs at least 47 µF with ESR between 100 mΩ and 10 Ω, and peak output current is internally limited. |
| 10 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 11 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 12 | NC | unconnected | Not connected. |
| 13 | NC | unconnected | Not connected. |
| 14 | NC | unconnected | Not connected. |
| 15 | NC | unconnected | Not connected. |
| 16 | NC | unconnected | Not connected. |
| 17 | GND | power_in | Ground reference for the regulator. |
| 18 | NC | unconnected | Not connected. |
| 19 | NC | unconnected | Not connected. |
| 20 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS75418QPWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps75418qpwpr-etched.step/tps75418qpwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps75418qpwpr.step/tps75418qpwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
ddac75f3b3fd04bf, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).